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    參數(shù)資料
    

    


    


    
型號(hào)：
XCS05-3PC240I

    

    
廠商：
Xilinx, Inc.

    

    
英文描述：
Spartan and Spartan-XL Families Field Programmable Gate Arrays

    

    
中文描述：
斯巴達(dá)和Spartan - xL的家庭現(xiàn)場(chǎng)可編程門陣列

    

    
文件頁(yè)數(shù)：
18/66頁(yè)

    

    
文件大?。?/td>
809K

    

    
代理商：
XCS05-3PC240I


    

    

    

	
    
    
    

    
    
	
    R
    Spartan and Spartan-XL Families Field Programmable Gate Arrays
    4-18
    DS060 (v1.5) March 2, 2000
    On-Chip Oscillator
    Spartan/XL devices include an internal oscillator. This
    oscillator is used to clock the power-on time-out, for config-
    uration memory clearing, and as the source of CCLK in
    Master configuration mode. The oscillator runs at a nominal
    8 MHz frequency that varies with process, V
    CC
    , and tem-
    perature. The output frequency falls between 4 MHz and
    10 MHz. 
    The oscillator output is optionally available after configura-
    tion. Any two of four resynchronized taps of a built-in divider
    are also available. These taps are at the fourth, ninth, four-
    teenth and nineteenth bits of the divider. Therefore, if the
    primary oscillator output is running at the nominal 8 MHz,
    the user has access to an 8-MHz clock, plus any two of
    500 kHz, 16 kHz, 490 Hz and 15 Hz. These frequencies
    can vary by as much as -50% or +25%.
    These signals can be accessed by placing the OSC4
    library element in a schematic or in HDL code. The oscilla-
    tor is automatically disabled after configuration if the OSC4
    symbol is not used in the design.
    Global Signals: GSR and GTS
    Global Set/Reset
    A separate Global Set/Reset line, as shown in 
    Figure 3 on
    page 4
     for the CLB and 
    Figure 6 on page 5
     for the IOB, sets
    or clears each flip-flop during power-up, reconfiguration, or
    when a dedicated Reset net is driven active. This global net
    (GSR) does not compete with other routing resources; it
    uses a dedicated distribution network. 
    Each flip-flop is configured as either globally set or reset in
    the same way that the local set/reset (SR) is specified.
    Therefore, if a flip-flop is set by SR, it is also set by GSR.
    Similarly, if in reset mode, it is reset by both SR and GSR.
    GSR can be driven from any user-programmable pin as a
    global reset input. To use this global net, place an input pad
    and input buffer in the schematic or HDL code, driving the
    GSR pin of the STARTUP symbol. (See 
    Figure 19
    .) A spe-
    cific pin location can be assigned to this input using a LOC
    attribute or property, just as with any other user-program-
    mable pad. An inverter can optionally be inserted after the
    input buffer to invert the sense of the GSR signal. Alterna-
    tively, GSR can be driven from any internal node.
    Global 3-State 
    A separate Global 3-state line (GTS) as shown in 
    Figure 5
    on page 6
     forces all FPGA outputs to the high-impedance
    state, unless boundary scan is enabled and is executing an
    EXTEST instruction. GTS does not compete with other
    routing resources; it uses a dedicated distribution network.
    GTS can be driven from any user-programmable pin as a
    global 3-state input. To use this global net, place an input
    pad and input buffer in the schematic or HDL code, driving
    the GTS pin of the STARTUP symbol. This is similar to what
    is shown in 
    Figure 19
     for GSR except the IBUF would be
    connected to GTS. A specific pin location can be assigned
    to this input using a LOC attribute or property, just as with
    any other user-programmable pad. An inverter can option-
    ally be inserted after the input buffer to invert the sense of
    the Global 3-state signal. Alternatively, GTS can be driven
    from any internal node.
    Boundary Scan
    The "bed of nails" has been the traditional method of testing
    electronic assemblies. This approach has become less
    appropriate, due to closer pin spacing and more sophisti-
    cated assembly methods like surface-mount technology
    and multi-layer boards. The IEEE Boundary Scan Standard
    1149.1 was developed to facilitate board-level testing of
    electronic assemblies. Design and test engineers can
    embed a standard test logic structure in their device to
    achieve high fault coverage for I/O and internal logic. This
    structure is easily implemented with a four-pin interface on
    any boundary scan compatible device. IEEE 1149.1-com-
    patible devices may be serial daisy-chained together, con-
    nected in parallel, or a combination of the two.
    The Spartan and Spartan-XL families implement IEEE
    1149.1-compatible BYPASS, PRELOAD/SAMPLE and
    EXTEST boundary scan instructions.   When the boundary
    scan configuration option is selected, three normal user I/O
    pins become dedicated inputs for these functions. Another
    user output pin becomes the dedicated boundary scan out-
    put. The details of how to enable this circuitry are covered
    later in this section.
    By exercising these input signals, the user can serially load
    commands and data into these devices to control the driv-
    ing of their outputs and to examine their inputs. This
    method is an improvement over bed-of-nails testing. It
    avoids the need to over-drive device outputs, and it reduces
    the user interface to four pins. An optional fifth pin, a reset
    for the control logic, is described in the standard but is not
    implemented in the Spartan/XL devices. 
    The dedicated on-chip logic implementing the IEEE 1149.1
    functions includes a 16-state machine, an instruction regis-
    ter and a number of data registers. The functional details
    can be found in the IEEE 1149.1 specification and are also
    discussed in the Xilinx application note: "
    Boundary Scan in
    FPGA Devices
    ." 
    PAD
    IBUF
    GSR
    GTS
    CLK DONEIN
    Q1Q4
    Q2
    Q3
    STARTUP
    X5260
    Figure 19:   Schematic Symbols for Global Set/Reset
    Powered by ICminer.com Electronic-Library Service CopyRight 2003
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
XCS05-3PC256C
Spartan and Spartan-XL Families Field Programmable Gate Arrays

    

    
XCS05-3PC256I
Spartan and Spartan-XL Families Field Programmable Gate Arrays

    

    
XCS05-3PC280C
Spartan and Spartan-XL Families Field Programmable Gate Arrays

    

    
XCS05-3PC280I
Spartan and Spartan-XL Families Field Programmable Gate Arrays

    

    
XCS05-3PC84C
Spartan and Spartan-XL Families Field Programmable Gate Arrays

    

    

    

    


    


    

    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
XCS05-3PC256C
 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays

    

    
XCS05-3PC256I
 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays

    

    
XCS05-3PC280C
 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays

    

    
XCS05-3PC280I
 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays

    

    
XCS05-3PC84
 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays

    

    
    
    
    
	
    	
    
    
     
     
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