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| 型號(hào)： | XCS05-3CS84I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場(chǎng)可編程門陣列 |
| 文件頁數(shù)： | 47/66頁 |
| 文件大小： | 809K |
| 代理商： | XCS05-3CS84I |
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R
DS060 (v1.5) March 2, 2000
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4-47
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Spartan-XL CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System)
and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
Spartan-XL devices and expressed in nanoseconds unless otherwise noted.
Speed Grade
Description
-5
-4
Units
Symbol
Min
Max
Min
Max
Clocks
Clock High time
Clock Low time
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H to X/Y outputs
F/G inputs via transparent latch to Q outputs
C inputs via H1 via H to X/Y outputs
Sequential Delays
Clock K to Flip-Flop or latch outputs Q
Setup Time before Clock K
F/G inputs
F/G inputs via H
Hold Time after Clock K
All Hold times, all devices
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q
Global Set/Reset
Delay from GSR input to any Q
Toggle Frequency (MHz)
(for export control purposes)
T
CH
T
CL
2.0
2.0
2.3
2.3
ns
ns
T
ILO
T
IHO
T
ITO
T
HH1O
1.0
1.7
1.5
1.5
1.1
2.0
1.8
1.8
ns
ns
ns
ns
T
CKO
1.2
1.4
ns
T
ICK
T
IHCK
0.6
1.3
0.7
1.6
ns
ns
0.0
0.0
ns
T
RPW
T
RIO
2.5
2.3
2.8
2.7
ns
ns
T
MRW
T
MRQ
F
TOG
10.5
See
page 51
for T
RRI
values per device.
250
11.5
ns
217
MHz
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