參數(shù)資料
型號： XCS05-3CS280I
廠商： Xilinx, Inc.
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： 斯巴達和Spartan - xL的家庭現(xiàn)場可編程門陣列
文件頁數(shù)： 20/66頁
文件大?。?/td> 809K
代理商： XCS05-3CS280I
R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
4-20
DS060 (v1.5) March 2, 2000
Table 12: Boundary Scan Instructions
Bit Sequence
The bit sequence within each IOB is: In, Out, 3-state. The
input-only pins contribute only the In bit to the boundary
scan I/O data register, while the output-only pins contrib-
utes all three bits.
The first two bits in the I/O data register are TDO.T and
TDO.O, which can be used for the capture of internal sig-
nals. The final bit is BSCANT.UPD, which can be used to
drive an internal net. These locations are primarily used by
Xilinx for internal testing.
From a cavity-up view of the chip (as shown in the FPGA
Editor), starting in the upper right chip corner, the boundary
scan data-register bits are ordered as shown in
Figure 21
.
The device-specific pinout tables for the Spartan/XL
devices include the boundary scan locations for each IOB
pin.
Including Boundary Scan in a Design
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