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| 型號： | XCS05-3CS256I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 38/66頁 |
| 文件大小： | 809K |
| 代理商： | XCS05-3CS256I |
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
4-38
DS060 (v1.5) March 2, 2000
Spartan CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Spartan
devices and are expressed in nanoseconds unless otherwise noted.
Single Port RAM
Speed Grade
-4
-3
Units
Size
Symbol
Min
Max
Min
Max
Write Operation
Address write cycle time (clock K period)
16x2
32x1
T
WCS
T
WCTS
8.0
8.0
11.6
11.6
ns
ns
Clock K pulse width (active edge)
16x2
32x1
T
WPS
T
WPTS
4.0
4.0
5.8
5.8
ns
ns
Address setup time before clock K
16x2
32x1
T
ASS
T
ASTS
1.5
1.5
2.0
2.0
ns
ns
Address hold time after clock K
16x2
32x1
T
AHS
T
AHTS
0.0
0.0
0.0
0.0
ns
ns
DIN setup time before clock K
16x2
32x1
T
DSS
T
DSTS
1.5
1.5
2.7
1.7
ns
ns
DIN hold time after clock K
16x2
32x1
T
DHS
T
DHTS
0.0
0.0
0.0
0.0
ns
ns
WE setup time before clock K
16x2
32x1
T
WSS
T
WSTS
1.5
1.5
1.6
1.6
ns
ns
WE hold time after clock K
16x2
32x1
T
WHS
T
WHTS
0.0
0.0
0.0
0.0
ns
ns
Data valid after clock K
16x2
32x1
T
WOS
T
WOTS
6.5
7.0
7.9
9.3
ns
ns
Read Operation
Address read cycle time
16x2
32x1
T
RC
T
RCT
2.6
3.8
2.6
3.8
ns
ns
Data Valid after address change (no Write
Enable)
16x2
32x1
T
ILO
T
IHO
1.2
2.0
1.6
2.7
ns
ns
Address setup time before clock K
16x2
32x1
T
ICK
T
IHCK
1.8
2.9
2.4
3.9
ns
ns
Note: Timing for 16 x 1 RAM option is identical to 16 x 2 RAM timing.
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| XCS05-3CS280C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| XCS05-3CS280C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3CS280I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3CS84C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3CS84I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3PC100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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