參數(shù)資料
型號(hào)： XCS05-3CS240I
廠商： Xilinx, Inc.
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場(chǎng)可編程門陣列
文件頁(yè)數(shù)： 27/66頁(yè)
文件大?。?/td> 809K
代理商： XCS05-3CS240I
R
DS060 (v1.5) March 2, 2000
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4-27
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Setting CCLK Frequency
In Master mode, CCLK can be generated in either of two
frequencies. In the default slow mode, the frequency
ranges from 0.5 MHz to 1.25 MHz for Spartan/XL devices.
In fast CCLK mode, the frequency ranges from 4 MHz to
10 MHz for Spartan/XL devices. The frequency is changed
to fast by an option when running the bitstream generation
software.
Data Stream Format
The data stream ("bitstream") format is identical for both
serial configuration modes, but different for the Spartan-XL
Express mode. In Express mode, the device becomes
active when DONE goes High, therefore no length count is
required. Additionally, CRC error checking is not supported
in Express mode. The data stream format is shown in
Table 16
. Bit-serial data is read from left to right. Express
mode data is shown with D0 at the left and D7 at the right.
The configuration data stream begins with a string of eight
ones, a preamble code, followed by a 24-bit length count
and a separator field of ones (or 24 fill bits, in Spartan-XL
Express mode). This header is followed by the actual con-
figuration data in frames. The length and number of frames
depends on the device type (see
Table 17
). Each frame
begins with a start field and ends with an error check. In
serial modes, a postamble code is required to signal the
end of data for a single device. In all cases, additional
start-up bytes of data are required to provide four clocks for
the startup sequence at the end of configuration. Long
daisy chains require additional startup bytes to shift the last
data through the chain. All start-up bytes are "don
’
t cares".
Description
Symbol
T
IC
T
DC
T
CD
T
CCH
T
CCL
F
CC
Min
5
20
0
45
45
Max
Units
μ
s
ns
ns
ns
ns
MHz
CCLK
INIT (High) setup time
D0 - D7 setup time
D0 - D7 hold time
CCLK High time
CCLK Low time
CCLK Frequency
1
2
3
10
X6710_m
BYTE
0
CCLK
FPGA Filled
1
2
3
INIT
TDC
TCD
TIC
D0-D7
DOUT
BYTE
1
BYTE
6
Header Received
Note: If not driven by the preceding DOUT, CS1
must
remain High until the device is fully configured.
Figure 28: Express Mode Programming Switching Characteristics
相關(guān)PDF資料
PDF描述
XCS05-3CS256C Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05-3CS256I Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05-3CS280C Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05-3CS280I Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05-3CS84C Spartan and Spartan-XL Families Field Programmable Gate Arrays
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XCS05-3CS256C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05-3CS256I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05-3CS280C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05-3CS280I 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS05-3CS84C 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
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