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參數(shù)資料
| 型號： | XCS05-3CS100I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達和Spartan - xL的家庭現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 24/66頁 |
| 文件大?。?/td> | 809K |
| 代理商： | XCS05-3CS100I |
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
4-24
DS060 (v1.5) March 2, 2000
Slave Serial Mode
In Slave Serial mode, the FPGA receives serial configura-
tion data on the rising edge of CCLK and, after loading its
configuration, passes additional data out, resynchronized
on the next falling edge of CCLK.
In this mode, an external signal drives the CCLK input of
the FPGA (most often from a Master Serial device). The
serial configuration bitstream must be available at the DIN
input of the lead FPGA a short setup time before each ris-
ing CCLK edge.
The lead FPGA then presents the preamble data
—
and all
data that overflows the lead device
—
on its DOUT pin.
There is an internal delay of 0.5 CCLK periods, which
means that DOUT changes on the falling CCLK edge, and
the next FPGA in the daisy chain accepts data on the sub-
sequent rising CCLK edge.
Figure 25
shows a full master/slave system. A Spartan/XL
device in Slave Serial mode should be connected as shown
in the third device from the left.
Slave Serial is the default mode if the Mode pins are left
unconnected, as they have weak pull-up resistors during
configuration.
Multiple slave devices with identical configurations can be
wired with parallel DIN inputs. In this way, multiple devices
can be configured simultaneously.
Serial Daisy Chain
Multiple devices with different configurations can be con-
nected together in a "daisy chain," and a single combined
bitstream used to configure the chain of slave devices.
To configure a daisy chain of devices, wire the CCLK pins
of all devices in parallel, as shown in
Figure 25
. Connect
the DOUT of each device to the DIN of the next. The lead or
master FPGA and following slaves each passes resynchro-
nized configuration data coming from a single source. The
header data, including the length count, is passed through
and is captured by each FPGA when it recognizes the 0010
preamble. Following the length-count data, each FPGA out-
puts a High on DOUT until it has received its required num-
ber of data frames.
After an FPGA has received its configuration data, it
passes on any additional frame start bits and configuration
data on DOUT. When the total number of configuration
clocks applied after memory initialization equals the value
of the 24-bit length count, the FPGAs begin the start-up
sequence and become operational together. FPGA I/O are
normally released two CCLK cycles after the last configura-
tion bit is received.
The daisy-chained bitstream is not simply a concatenation
of the individual bitstreams. The PROM File Formatter must
be used to combine the bitstreams for a daisy-chained con-
figuration.
Spartan
MASTER
SERIAL
Spartan
SLAVE
FPGA
SLAVE
XC17S00
PROGRAM
NOTE
:
M2, M1, M0 can be shorted
to V
CC
if not used as I/O
MODE
DOUT
CCLK
CLK
V
CC
+5V
DATA
CE
CEO
VPP
RESET/OE
DONE
DIN
LDC
INIT
INIT
DONE
PROGRAM
PROGRAM
D/P
INIT
RESET
CCLK
DIN
CCLK
DIN
DOUT
DOUT
MODE
M1
PWRDN
M0
M2
(Low Reset Option Used)
3.3K
3.3K
3.3K
3.3K
V
CC
S9025_02
N/C
Figure 25: Master/Slave Serial Mode Circuit Diagram
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相關PDF資料 |
PDF描述 |
|---|---|
| XCS05-3CS144C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3CS144I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3CS208C | Silver Mica Capacitor; Capacitance:100pF; Capacitance Tolerance:+/- 2%; Series:CD5; Voltage Rating:300VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:3mm; Leaded Process Compatible:Yes RoHS Compliant: Yes |
| XCS05-3CS208I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3CS240C | Silver Mica Capacitor; Capacitance:100pF; Capacitance Tolerance:+/- 5%; Series:CD5; Voltage Rating:300VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:3mm; Leaded Process Compatible:Yes RoHS Compliant: Yes |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XCS05-3CS144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3CS144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL FPGA |
| XCS05-3CS208C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3CS208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05-3CS240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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