參數(shù)資料
型號： XCS05-3BG84C
廠商： Xilinx, Inc.
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： 斯巴達和Spartan - xL的家庭現(xiàn)場可編程門陣列
文件頁數(shù)： 40/66頁
文件大小： 809K
代理商： XCS05-3BG84C
R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
4-40
DS060 (v1.5) March 2, 2000
Spartan Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report.
Spartan Output Flip-Flop, Clock-to-Out
Note 1: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Note 2: Output timing is measured at ~50% V
CC
threshold with 50 pF external capacitive load. For different loads, see
Figure 32
.
Capacitive Load Factor
Figure 32
shows the relationship between I/O output delay
and load capacitance. It allows a user to adjust the speci-
fied output delay if the load capacitance is different than
50 pF. For example, if the actual load capacitance is
120 pF, add 2.5 ns to the specified delay. If the load capac-
itance is 20 pF, subtract 0.8 ns from the specified output
delay.
Figure 32
is usable over the specified operating con-
ditions of voltage and temperature and is independent of
the output slew rate control.
Figure 32: Delay Factor at Various Capacitive Loads
3
Speed Grade
Description
Global Primary Clock to TTL Output using OFF
Fast
-4
-3
Units
Symbol
Device
Max
Max
T
ICKOF
XCS05
XCS10
XCS20
XCS30
XCS40
XCS05
XCS10
XCS20
XCS30
XCS40
5.3
5.7
6.1
6.5
6.8
9.0
9.4
9.8
10.2
10.5
8.7
9.1
9.3
9.4
10.2
11.5
12.0
12.2
12.8
12.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Slew-rate limited
T
ICKO
Global Secondary Clock to TTL Output using OFF
Fast
T
ICKSOF
XCS05
XCS10
XCS20
XCS30
XCS40
XCS05
XCS10
XCS20
XCS30
XCS40
5.8
6.2
6.6
7.0
7.3
9.5
9.9
10.3
10.7
11.0
9.2
9.6
9.8
9.9
10.7
12.0
12.5
12.7
13.2
14.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Slew-rate limited
T
ICKSO
Delay Adder for CMOS Outputs Option
Fast
Slew-rate Limited
OFF = Output Flip-Flop
T
CMOSOF
T
CMOSO
All devices
All devices
0.8
1.5
1.0
2.0
ns
ns
X8257
-2
0
20
40
Capacitance (pF)
60
80
D
100 120 140
-1
0
1
2
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