
R
XCR3320: 320 Macrocell SRAM CPLD
29
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DS033 (v1.3) October 9, 2000
This product has been discontinued. Please see
for details.Device Configuration Through JTAG
In addition to the normal configuration modes, the
XCR3320 can also be configured through the JTAG port.
This feature is very useful for design prototyping and debug
before the device is put into the final product. In System
Configuration of the XCR3320 is supported by Xilinx
PC-ISP software.
Table 14
shows the ISC commands sup-
ported by the XCR3320
To configure the device through the JTAG port, mode pins
M0, M1, and M2 should all be held low. M3, as always,
should be high and the JTAG pins should be terminated as
described in
“
Terminations
”
on page 8
of this data sheet.
Table 14: Low Level ISP Commands
Instruction
(Register Used)
Enable
(ISP Shift Register)
Instruction
Code
1001
Description
Enables the Erase, Program, and Verify commands. Using the ENABLE
instruction before the Erase, Program, and Verify instructions allows the user
to specify the outputs the device using the JTAG Boundary-Scan
SAMPLE/PRELOAD command.
Erases the entire EEPROM array. The outputs during this operation can be
defined by user by using the JTAG SAMPLE/PRELOAD command.
Programs the data in the ISP Shift Register into the addressed EEPROM row.
The outputs during this operation can be defined by user by using the JTAG
SAMPLE/PRELOAD command.
Transfers the data from the addressed row to the ISP Shift Register. The data
can then be shifted out and compared with the JEDEC file. The outputs during
this operation can be defined by the user.
Erase
(ISP Shift Register)
Program
(ISP Shift Register)
1010
1011
Verify
(ISP Shift Register)
1100