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參數(shù)資料
| 型號： | XCR3256XL-10CS280C |
| 廠商： | XILINX INC |
| 元件分類： | PLD |
| 英文描述： | 256 Macrocell CPLD |
| 中文描述： | EE PLD, 10 ns, PBGA280 |
| 封裝： | 0.80 MM PITCH, CSP-280 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 257K |
| 代理商： | XCR3256XL-10CS280C |
XCR3256XL 256 Macrocell CPLD
DS013 (v1.2) May 3, 2000
Preliminary Product Specification
1-800-255-7778RAC Electrical Characteristics Over Recommended Operating Conditions
(1,2)
Symbol
Parameter
-7
-10
-12
Unit
Min.
Max.
Min.
Max.
Min.
Max.
T
PD1
Propagation delay time (single p-term)
-
7.0
-
9.0
-
10.8
ns
T
PD2
Propagation delay time (OR array)
(3)
-
7.5
-
10.0
-
12.0
ns
T
CO
Clock to output (global synchronous pin clock)
-
4.5
-
5.8
-
6.9
ns
T
SUF
Setup time fast
2.0
-
2.5
-
3.0
-
ns
T
SU
Setup time
4.8
-
6.5
-
7.9
-
ns
T
H
Hold time
0
-
0
-
0
-
ns
T
WLH
Global clock pulse width (High or Low)
3.0
-
4.0
-
5.0
-
ns
T
PLH
P-term clock pulse width (High or Low)
4.5
-
6.0
-
7.5
-
ns
T
R
Input rise time
-
20
-
20
-
20
ns
T
L
Input fall time
-
20
-
20
-
20
ns
f
SYSTEM
Maximum system frequency
-
140
-
105
-
88
MHz
T
CONFIG
Configuration time
(4)
-
40
-
40
-
40
m
s
T
POE
P-term OE to output enabled
-
9.0
-
11.0
-
13.0
ns
T
POD
P-term OE to output disabled
(5)
-
9.0
-
11.0
-
13.0
ns
T
PCO
P-term clock to output
-
8.0
-
10.3
-
12.4
ns
T
PAO
P-term set/reset to output valid
-
9.0
-
11.0
-
13.0
ns
Notes:
1.
2.
3.
4.
5.
Specifications measured with one output switching.
See XPLA3 Family Data Sheet (DS012) for recommended operating conditions.
See
Figure 4
for derating.
Typical current draw during configuration is 10 mA at 3.6V.
Output C
L
= 5 pF.
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| XCR3256XL-10CSG280I | 制造商:Xilinx 功能描述:XLXXCR3256XL-10CSG280I IC SYSTEM GATE 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 6K GATES 256 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
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