參數(shù)資料
型號(hào)： XCR3128A-15VQ100I
廠(chǎng)商： XILINX INC
元件分類(lèi)： PLD
英文描述： CPLD with Enhanced Clocking
中文描述： EE PLD, 15 ns, PQFP100
封裝： PLASTIC, VQFP-100
文件頁(yè)數(shù)： 6/17頁(yè)
文件大?。?/td> 268K
代理商： XCR3128A-15VQ100I
R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
DS035 (v1.2) August 10, 2000
www.xilinx.com
1-800-255-7778
6
TotalCMOS Design Technique for Fast Zero
Power
Xilinx is the first to offer a TotalCMOS CPLD, both in pro-
cess technology and design technique. Xilinx employs a
cascade of CMOS gates to implement its Sum of Products
instead of the traditional sense amp approach. This CMOS
gate implementation allows Xilinx to offer CPLDs which are
both high-performance and low power, breaking the para-
digm that to have low power, you must have low perfor-
mance. Refer to
and
taken with eight up/down, loadable 16-bit counters at 3.3V,
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XCR3128A-7VQ100I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:CPLD with Enhanced Clocking
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