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參數資料
| 型號： | XCR3128A-10VQ100I |
| 廠商： | XILINX INC |
| 元件分類： | PLD |
| 英文描述： | CPLD with Enhanced Clocking |
| 中文描述： | EE PLD, 10 ns, PQFP100 |
| 封裝： | PLASTIC, VQFP-100 |
| 文件頁數： | 5/17頁 |
| 文件大?。?/td> | 268K |
| 代理商： | XCR3128A-10VQ100I |
R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
5
www.xilinx.com
1-800-255-7778
DS035 (v1.2) August 10, 2000
Simple Timing Model
shows the CoolRunner Timing Model. The Cool-including t
PD
, t
SU
, and t
CO
. In other competing architec-
tures, the user may be able to fit the design into the CPLD,
but is not sure whether system timing requirements can be
met until after the design has been fit into the device. This is
because the timing models of competing architectures are
very complex and include such things as timing dependen-
cies on the number of parallel expanders borrowed, shar-
able expanders, varying number of X and Y routing
channels used, etc. In the XPLA architecture, the user
knows up front whether the design will meet system timing
requirements. This is due to the simplicity of the timing
model.
Figure 4: CoolRunner Timing Model
OUTPUT PIN
INPUT PIN
SP00553
t
PD_PAL
= COMBINATORIAL PAL ONLY
t
PD_PLA
= COMBINATORIAL PAL + PLA
OUTPUT PIN
INPUT PIN
D
Q
REGISTERED
t
SU_PAL
= PAL ONLY
t
SU_PLA
= PAL + PLA
REGISTERED
t
CO
GLOBAL CLOCK PIN
相關PDF資料 |
PDF描述 |
|---|---|
| XCR3128A-10TQ128C | CPLD with Enhanced Clocking |
| XCR3128A-10TQ128I | CPLD with Enhanced Clocking |
| XCR3128A-12TQ128C | CPLD with Enhanced Clocking |
| XCR3128A-12TQ128I | CPLD with Enhanced Clocking |
| XCR3128A-12VQ100C | CPLD with Enhanced Clocking |
相關代理商/技術參數 |
參數描述 |
|---|---|
| XCR3128A-12TQ128C | 制造商:XILINX 制造商全稱:XILINX 功能描述:CPLD with Enhanced Clocking |
| XCR3128A-12TQ128I | 制造商:XILINX 制造商全稱:XILINX 功能描述:CPLD with Enhanced Clocking |
| XCR3128A-12VQ100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:CPLD with Enhanced Clocking |
| XCR3128A-12VQ100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:CPLD with Enhanced Clocking |
| XCR3128A-15TQ128C | 制造商:XILINX 制造商全稱:XILINX 功能描述:CPLD with Enhanced Clocking |
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