
XCR3064XL 64 Macrocell CPLD
DS017 (v1.6) January 8, 2002
Product Specification
1-800-255-7778 R Revision History
The following table shows the revision history for this document..
Date
Version
Revision
06/01/00
1.0
Initial Xilinx release.
08/30/00
1.1
Added 48-ball CS BGA package.
11/18/00
1.2
Updated to full production data sheet; corrected note in
Table 4
to read: "port enable pin is
brought High".
12/08/00
1.3
Added PC44 package.
04/11/01
1.4
Added Typical I/V curve,
Figure 2
; added
Table 2
: Total User I/O; changed V
OH
spec.
04/19/01
1.5
Updated Typical I/V curve,
Figure 2
: added voltage levels.
01/08/02
1.6
Moved I
CC
vs. Freq
Figure 1
and
Table 1
to page 1. Added single p-term setup time (T
SU1
)
to AC Table, renamed T
SU
to T
SU2
for setup time through the OR array. Updated T
SUF
and
T
FIN
spec to match software timing. Added T
INIT
spec. Updated T
CONFIG
spec. Updated T
HI
spec to correct a typo. Updated AC Load Circuit diagram to more closely resemble true test
conditions, added note for T
POD
delay measurement. Updated note 5 in AC Characteristics
table lowering typical current draw during configuration.