- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375008 > XCR3064A (Xilinx, Inc.) 64 Macrocell CPLD With Enhanced Clocking(帶增強(qiáng)時(shí)鐘控制的64宏單元復(fù)雜可編程邏輯器件) PDF資料下載
參數(shù)資料
| 型號(hào)： | XCR3064A |
| 廠商： | Xilinx, Inc. |
| 英文描述： | 64 Macrocell CPLD With Enhanced Clocking(帶增強(qiáng)時(shí)鐘控制的64宏單元復(fù)雜可編程邏輯器件) |
| 中文描述： | 64宏單元CPLD在增強(qiáng)時(shí)鐘（帶增強(qiáng)時(shí)鐘控制的64個(gè)宏單元復(fù)雜可編程邏輯器件） |
| 文件頁(yè)數(shù)： | 5/17頁(yè) |
| 文件大?。?/td> | 171K |
| 代理商： | XCR3064A |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)當(dāng)前第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)
R
XCR3064A: 64 Macrocell CPLD With Enhanced Clocking
5
www.xilinx.com
1-800-255-7778
DS037 (v1.3) October 9, 2000
This product has been discontinued. Please see
for details.Simple Timing Model
Figure 4
shows the CoolRunner Timing Model. The Cool-
Runner timing model looks very much like a 22V10 timing
model in that there are three main timing parameters,
including T
PD
,T
SU
, and T
CO
. In other architectures, the
user may be able to fit the design into the CPLD, but is not
sure whether system timing requirements can be met until
after the design has been fit into the device. This is
because the timing models of competing architectures are
very complex and include such things as timing dependen-
cies on the number of parallel expanders borrowed, shar-
able expanders, varying number of X and Y routing
channels used, etc. In the XPLA architecture, the user
knows up front whether the design will meet system timing
requirements. This is due to the simplicity of the timing
model. For example, in the XCR3064A device, the user
knows up front that if a given output uses 5product terms or
less, the T
PD
= 7.5 ns, the T
SU_PAL
= 3.5 ns, and the
T
CO
= 5.5 ns. If an output is using six to 37 product terms,
an additional 1.5 ns must be added to the T
PD
and T
SU
tim-
ing parameters to account for the time to propagate
through the PLA array.
TotalCMOS Design Technique for Fast Zero
Power
Xilinx is the first to offer a TotalCMOS
CPLD, both in pro-
cess technology and design technique. Xilinx employs a
cascade of CMOS gates to implement its Sum of Products
instead of the traditional sense amp approach. This CMOS
gate implementation allows Xilinx to offer CPLDs which are
both high performance and low power, breaking the para-
digm that to have low power, you must have low perfor-
mance. Refer to
Figure 5
and
Table 1
showing the I
CC
vs.
Frequency of our XCR3064A TotalCMOS CPLD. (Data
taken with four up/down loadable 16-bit counters at 3.3V,
25
°
C)
Figure 4: CoolRunner Timing Model
OUTPUT PIN
INPUT PIN
SP00441
T
PD_PAL
= COMBINATORIAL PAL ONLY
T
PD_PLA
= COMBINATORIAL PAL + PLA
T
T
T
OUTPUT PIN
INPUT PIN
D
Q
REGISTERED
SU_PAL
= PAL ONLY
SU_PLA
= PAL + PLA
REGISTERED
CO
GLOBAL CLOCK PIN
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCR3064XL-6CP56C | XCR3064XL 64 Macrocell CPLD |
| XCR3064XL-10VQ100I | XCR3064XL 64 Macrocell CPLD |
| XCR3064XL-10VQ44C | XCR3064XL 64 Macrocell CPLD |
| XCR3064XL-10VQ44I | XCR3064XL 64 Macrocell CPLD |
| XCR3064XL-6VQ44C | XCR3064XL 64 Macrocell CPLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCR3064A-10CP56C | 制造商:XILINX 制造商全稱:XILINX 功能描述:64 Macrocell CPLD With Enhanced Clocking |
| XCR3064A-10PC44C | 制造商:XILINX 制造商全稱:XILINX 功能描述:64 Macrocell CPLD With Enhanced Clocking |
| XCR3064A-10PC44I | 制造商:Xilinx 功能描述: |
| XCR3064A-10VQ100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:64 Macrocell CPLD With Enhanced Clocking |
| XCR3064A-10VQ44C | 制造商:XILINX 制造商全稱:XILINX 功能描述:64 Macrocell CPLD With Enhanced Clocking |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。