- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372880 > XCR3032XL-10PC44I (XILINX INC) XCR3032XL 32 Macrocell CPLD PDF資料下載
參數(shù)資料
| 型號(hào)： | XCR3032XL-10PC44I |
| 廠商： | XILINX INC |
| 元件分類： | PLD |
| 英文描述： | XCR3032XL 32 Macrocell CPLD |
| 中文描述： | EE PLD, 10 ns, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 84K |
| 代理商： | XCR3032XL-10PC44I |
DS023 (v1.5) January 8, 2002
Preliminary Product Specification
1-800-255-77781
2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm
.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
Lowest power 32 macrocell CPLD
5.0 ns pin-to-pin logic delays
System frequencies up to 200 MHz
32 macrocells with 750 usable gates
Available in small footprint packages
-
48-ball CS BGA (36 user I/O pins)
-
44-pin VQFP (36 user I/O)
-
44-pin PLCC (36 user I/O)
Optimized for 3.3V systems
-
Ultra-low power operation
-
5V tolerant I/O pins with 3.3V core supply
-
Advanced 0.35 micron five layer metal EEPROM
process
-
Fast Zero Power (FZP) CMOS design
technology
Advanced system features
-
In-system programming
-
Input registers
-
Predictable timing model
-
Up to 23 available clocks per function block
-
Excellent pin retention during design changes
-
Full IEEE Standard 1149.1 boundary-scan (JTAG)
-
Four global clocks
-
Eight product term control terms per function block
Fast ISP programming times
Port Enable pin for dual function of JTAG ISP pins
2.7V to 3.6V supply voltage at industrial temperature
range
Programmable slew rate control per macrocell
Security bit prevents unauthorized access
Refer to XPLA3 family data sheet (
DS012
) for
architecture description
Description
The XCR3032XL is a 3.3V, 32-macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of two function blocks provide
750 usable gates. Pin-to-pin propagation delays are 5.0 ns
with a maximum system frequency of 200 MHz.
TotalCMOS Design Technique for Fast
Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple-
mentation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
Figure 1
and
Table 1
showing the I
CC
vs. Frequency of our
XCR3032XL TotalCMOS CPLD (data taken with two
°
C).
0
XCR3032XL 32 Macrocell CPLD
DS023 (v1.5) January 8, 2002
0
14
Preliminary Product Specification
R
Figure 1:
I
CC
vs. Frequency at V
CC
= 3.3V, 25°C
5
0
10
15
20
0
20
40
60
80
100
120
140
160
180
200
Frequency (MHz)
DS023_01_080101
T
C
(
Table 1:
I
CC
vs. Frequency
(V
CC
= 3.3V, 25
°
C)
Frequency (MHz)
Typical I
CC
(mA)
0
1
5
10
1.06
20
2.09
50
5.2
100
10.26
200
20.3
0.02
0.13
0.54
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCR3032XL-5CS48C | XCR3032XL 32 Macrocell CPLD |
| XCR3032XL-5CS48I | XCR3032XL 32 Macrocell CPLD |
| XCR3032XL-5PC44C | XCR3032XL 32 Macrocell CPLD |
| XCR3032XL-5PC44I | XCR3032XL 32 Macrocell CPLD |
| XCR3032XL-5VQ44C | XCR3032XL 32 Macrocell CPLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCR3032XL-10VQ44C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 750 GATES 32 MCRCLLS 125MHZ 0.35UM 3.3 - Trays |
| XCR3032XL-10VQ44I | 功能描述:IC CPLD 3.3V ZERO PWR 44-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:CoolRunner XPLA3 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門(mén)數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤(pán) |
| XCR3032XL-10VQ44Q | 制造商:Rochester Electronics LLC 功能描述: 制造商:Xilinx 功能描述: |
| XCR3032XL-10VQ44Q0789 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Xilinx 功能描述: |
| XCR3032XL-10VQG44C | 功能描述:IC ISP CPLD 32 MCELL3.3V 44-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:CoolRunner XPLA3 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門(mén)數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤(pán) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。