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參數(shù)資料
| 型號： | XCR3032-8VQ44I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | 32 Macrocell CPLD |
| 中文描述： | 32宏單元CPLD |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 209K |
| 代理商： | XCR3032-8VQ44I |
R
XCR3032: 32 Macrocell CPLD
5
www.xilinx.com
1-800-255-7778
DS038 (v1.3) October 9, 2000
This product has been discontinued. Please see
www.xilinx.com/partinfo/notify/pdn0007.htm
for details.
Simple Timing Model
Figure 5
shows the CoolRunner Timing Model. The Cool-
Runner timing model looks very much like a 22V10 timing
model in that there are three main timing parameters,
including t
PD
, t
SU
, and t
CO
. In other architectures, the user
may be able to fit the design into the CPLD, but is not sure
whether system timing requirements can be met until after
the design has been fit into the device. This is because the
timing models of competing architectures are very complex
and include such things as timing dependencies on the
number of parallel expanders borrowed, sharable expand-
ers, varying number of X and Y routing channels used, etc.
In the XPLA architecture, the user knows up front whether
the design will meet system timing requirements. This is
due to the simplicity of the timing model. For example, in
the XCR3032 device, the user knows up front that if a given
output uses five product terms or less, the t
PD
= 8 ns, the
t
SU
= 6.5 ns, and the t
CO
= 7.5 ns. If an output is using six to
37 product terms, an additional 2.5 ns must be added to the
t
PD
and t
SU
timing parameters to account for the time to
propagate through the PLA array.
TotalCMOS Design Technique for Fast Zero
Power
Xilinx is the first to offer a TotalCMOS CPLD, both in pro-
cess technology and design technique. Xilinx employs a
cascade of CMOS gates to implement its Sum of Products
instead of the traditional sense amp approach. This CMOS
gate implementation allows Xilinx to offer CPLDs which are
both high performance and low power, breaking the para-
digm that to have low power, you must have low perfor-
mance. Refer to
Figure 6
and
Table 1
showing the I
CC
vs.
Frequency of our XCR3032 TotalCMOS CPLD.
Figure 4: CoolRunner Timing Model
OUTPUT PIN
INPUT PIN
SP00441
t
PD_PAL
= COMBINATORIAL PAL ONLY
t
PD_PLA
= COMBINATORIAL PAL + PLA
OUTPUT PIN
INPUT PIN
D
Q
REGISTERED
t
SU_PAL
= PAL ONLY
t
SU_PLA
= PAL + PLA
REGISTERED
t
CO
GLOBAL CLOCK PIN
xcr3032.fm Page 5 Monday, October 9, 2000 6:44 PM
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|---|---|
| XCR3032C-12VQ44I | 制造商:Xilinx 功能描述: |
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| XCR3032XL-10CS48I | 功能描述:IC CPLD 3.3V ZERO PWR 48-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復雜可編程邏輯器件） 系列:CoolRunner XPLA3 標準包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內可編程 最大延遲時間 tpd(1):7.1ns 電壓電源 - 內部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應商設備封裝:208-PQFP（28x28） 包裝:托盤 |
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