- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375008 > XCR3032-8VQ44C (XILINX INC) 32 Macrocell CPLD PDF資料下載
參數(shù)資料
| 型號： | XCR3032-8VQ44C |
| 廠商： | XILINX INC |
| 元件分類： | PLD |
| 英文描述： | 32 Macrocell CPLD |
| 中文描述： | EE PLD, 10.5 ns, PQFP44 |
| 封裝： | PLASTIC, VQFP-44 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 209K |
| 代理商： | XCR3032-8VQ44C |
R
XCR3032: 32 Macrocell CPLD
9
www.xilinx.com
1-800-255-7778
DS038 (v1.3) October 9, 2000
This product has been discontinued. Please see
www.xilinx.com/partinfo/notify/pdn0007.htm
for details.
AC Electrical Characteristics
1
For Commercial Grade Devices
Commercial: 0
°
C
≤
T
AMB
≤
+ 70
°
C; 3.0V
≤
V
CC
≤
3.6V
Symbol
Parameter
8
10
12
Unit
Min. Max. Min. Max. Min. Max.
2
8
2
t
PD_PAL
Propagation delay time, input (or feedback node) to output through
PAL
Propagation delay time, input (or feedback node) to output through
PAL + PLA
Clock to out (global synchronous clock from pin)
Setup time (from input or feedback node) through PAL
Setup time (from input or feedback node) through PAL + PLA
Hold time
Clock High time
Clock Low time
Input rise time
Input fall time
Maximum FF toggle rate
2
(1/t
CH
+ t
CL
)
Maximum internal frequency
2
(1/t
SUPAL
+ t
CF
)
Maximum external frequency
2
(1/t
SUPAL
+ t
CO
)
Output buffer delay time
t
PDF_PAL
Input (or feedback node) to internal feedback node delay time
through PAL
t
PDF_PLA
Input (or feedback node) to internal feedback node delay time
through PAL + PLA
t
CF
Clock to internal feedback node delay time
t
INIT
Delay from valid V
CC
to valid reset
t
ER
t
EA
Input to output valid
t
RP
Input to register preset
t
RR
Input to register reset
Notes:
1. Specifications measured with one output switching. See
Figure 6
and
Table 2
for derating.
2 . This parameter guaranteed by design and characterization, not by test.
3. Output C
L
= 5 pF.
10
2
12
ns
t
PD_PLA
3
10.5
3
13
3
15
ns
t
CO
t
SU_PAL
t
SU_PLA
t
H
t
CH
t
CL
t
R
t
F
f
MAX1
f
MAX2
f
MAX3
t
BUF
2
7
2
9
2
11
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
6.5
9
8.5
11.5
10.5
13.5
0
0
0
3
3
4
4
5
5
20
20
20
20
20
20
167
83
74
125
63
57
100
50
47
1.5
6.5
1.5
8.5
1.5
10.5
9
11.5
13.5
ns
5.5
50
15
15
16
19
7.5
50
17
17
18
21
9.5
50
19
19
20
23
ns
μ
s
ns
ns
ns
ns
Input to output disable
3
xcr3032.fm Page 9 Monday, October 9, 2000 6:44 PM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCR3032-8VQ44I | 32 Macrocell CPLD |
| XCR3064A | 64 Macrocell CPLD With Enhanced Clocking(帶增強時鐘控制的64宏單元復(fù)雜可編程邏輯器件) |
| XCR3064XL-6CP56C | XCR3064XL 64 Macrocell CPLD |
| XCR3064XL-10VQ100I | XCR3064XL 64 Macrocell CPLD |
| XCR3064XL-10VQ44C | XCR3064XL 64 Macrocell CPLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCR3032-8VQ44I | 制造商:XILINX 制造商全稱:XILINX 功能描述:32 Macrocell CPLD |
| XCR3032C-12VQ44I | 制造商:Xilinx 功能描述: |
| XCR3032XL | 制造商:XILINX 制造商全稱:XILINX 功能描述:XCR3032XL 32 Macrocell CPLD |
| XCR3032XL-10 | 制造商:XILINX 制造商全稱:XILINX 功能描述:XCR3032XL 32 Macrocell CPLD |
| XCR3032XL-10CS48C | 制造商:Xilinx 功能描述:CPLD COOLRUNNER XPLA3 750 GATES 32 MCRCLLS 125MHZ 0.35UM 3.3 - Trays 制造商:Xilinx 功能描述:XLXXCR3032XL-10CS48C IC SYSTEM GATE |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。