- 您現在的位置：買賣IC網 > PDF目錄19909 > XCF02SVO20C (Xilinx Inc)IC PROM IN SYST PRG 3.3V 20TSSOP PDF資料下載
參數資料
| 型號： | XCF02SVO20C |
| 廠商： | Xilinx Inc |
| 文件頁數： | 2/35頁 |
| 文件大小： | 0K |
| 描述： | IC PROM IN SYST PRG 3.3V 20TSSOP |
| 標準包裝： | 74 |
| 可編程類型： | 系統內可編程 |
| 存儲容量： | 2Mb |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 20-TSSOP |
| 包裝： | 管件 |
第1頁當前第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁
Platform Flash In-System Programmable Configuration PROMs
DS123 (v2.18) May 19, 2010
Product Specification
10
R
Initiating FPGA Configuration
The options for initiating FPGA configuration via the
Platform Flash PROM include:
Automatic configuration on power up
Applying an external pulse to the FPGA PROGRAM_B
pin
Applying the JTAG CONFIG instruction to the PROM
Following the FPGA’s power-on sequence or the assertion
of the PROGRAM_B pin, the FPGA’s configuration memory
is cleared, the configuration mode is selected, and the
FPGA is ready to accept a new configuration bitstream. The
FPGA’s PROGRAM_B pin can be controlled by an external
source, or alternatively, the Platform Flash PROMs
incorporate a CF pin that can be tied to the FPGA’s
PROGRAM_B pin. Executing the CONFIG instruction
through JTAG pulses the CF output Low once for
300-500 ns, resetting the FPGA and initiating configuration.
The iMPACT software can issue the JTAG CONFIG
command to initiate FPGA configuration by setting the
“Load FPGA” option.
When using the XCFxxP Platform Flash PROM with design
revisioning enabled, the CF pin should always be connected
to the PROGRAM_B pin on the FPGA to ensure that the
current design revision selection is sampled when the
FPGA is reset. The XCFxxP PROM samples the current
design revision selection from the external REV_SEL pins
or the internal programmable Revision Select bits on the
rising edge of CF. When the JTAG CONFIG command is
executed, the XCFxxP samples the new design revision
selection before initiating the FPGA configuration
sequence. When using the XCFxxP Platform Flash PROM
without design revisioning, if the CF pin is not connected to
the FPGA PROGRAM_B pin, then the XCFxxP CF pin must
be tied High.
X-Ref Target - Figure 5
Figure 5: Design Revision Storage Examples
REV 0
(8 Mbits)
REV 1
(8 Mbits)
REV 2
(8 Mbits)
REV 3
(8 Mbits)
REV 0
(8 Mbits)
REV 1
(8 Mbits)
REV 2
(16 Mbits)
REV 0
(16 Mbits)
REV 1
(16 Mbits)
REV 0
(8 Mbits)
REV 1
(24 Mbits)
REV 0
(32 Mbits)
4 Design Revisions
3 Design Revisions
2 Design Revisions
1 Design Revision
(a) Design Revision storage examples for a single XCF32P PROM
REV 0
(16 Mbits)
REV 1
(16 Mbits)
REV 2
(16 Mbits)
REV 3
(16 Mbits)
REV 0
(16 Mbits)
REV 1
(16 Mbits)
REV 2
(32 Mbits)
REV 0
(32 Mbits)
REV 1
(32 Mbits)
REV 0
(16 Mbits)
REV 1
(16 Mbits)
REV 0
(32 Mbits)
4 Design Revisions
3 Design Revisions
2 Design Revisions
1 Design Revision
(b) Design Revision storage examples spanning two XCF32P PROMs
PROM 0
REV 0
(32 Mbits)
REV 1
(32 Mbits)
PROM 1
ds123_20_102103
相關PDF資料 |
PDF描述 |
|---|---|
| V24C28H100BL3 | CONVERTER MOD DC/DC 28V 100W |
| ACC25DRYH-S734 | CONN EDGECARD 50POS DIP .100 SLD |
| V24C28H100BL | CONVERTER MOD DC/DC 28V 100W |
| RBB106DHRT-S621 | CONN EDGECARD EXTEND 212POS .050 |
| V48C5H100B | CONVERTER MOD DC/DC 5V 100W |
相關代理商/技術參數 |
參數描述 |
|---|---|
| XCF02SVO20C0100 | 制造商:Xilinx 功能描述:IC SYSTEM GATE |
| XCF02SVO20C0936 | 制造商:Xilinx 功能描述:IC SYSTEM GATE |
| XCF02S-VO20CES | 制造商:Xilinx 功能描述: |
| XCF02SVO48 | 制造商:XILINX 制造商全稱:XILINX 功能描述:Platform Flash In-System Programmable Configuration PROMS |
| XCF02SVOG20C | 功能描述:IC PROM SRL FOR 2M GATE 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 - 用于 FPGA 的配置 Proms 系列:- 產品變化通告:Product Discontinuation 28/Jul/2010 標準包裝:98 系列:- 可編程類型:OTP 存儲容量:300kb 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-TSOP 包裝:管件 |
發(fā)布緊急采購，3分鐘左右您將得到回復。