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參數(shù)資料
| 型號(hào)： | XCCACEM64SERIES |
| 英文描述： | System ACE MPM Solution |
| 中文描述： | 系統(tǒng)ACE MPM的解決方案 |
| 文件頁數(shù)： | 24/29頁 |
| 文件大小： | 285K |
| 代理商： | XCCACEM64SERIES |
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IEEE 1149.1 Boundary Scan
The Xilinx Virtex-E XCV50E and XC18V01 PROMs in the
System ACE MPM support IEEE 1149.1 Boundary Scan.
Although the AMD Flash memory does not support Bound-
ary Scan, all signal pins on the AMD Flash memory and the
MPM BG388 package are connected to boundary scanna-
ble pins on the XCV50E device (with the exception of the
XCCACEM64
’
s ACC pin). Thus, the System ACE MPM sup-
ports Boundary Scan for all significant signals on the Sys-
tem ACE MPM via the XCV50E
’
s Boundary Scan register.
Although the XC18V01 supports a Boundary Scan register,
most of its signals are solely internal to the System ACE
MPM. Signals from the XC18V01 device that reach the
external BG388 sites are redundantly tied to the XCV50E
device. Thus, Boundary Scan can be effectively performed
solely with the XCV50E Boundary Scan functions. See
Figure 13
.
Boundary Scan Test Requirements
The System ACE MPM FCMRESET signal drives the
XCV50E /PROGRAM pin. The active-Low PROGRAM pin
on the XCV50E device resets the XCV50E
’
s Boundary
Scan test access port (TAP) controller. The FCM_ENABLE
signal must not be driven Low during Boundary Scan test.
Boundary Scan test functionality is undefined during the
System ACE MPM initialization phase. Therefore, boundary
scan testing must wait until after the initialization phase is
complete.
A special System ACE MPM Boundary Scan description
language (BSDL) file is required for proper Boundary Scan
test operation with the Virtex-E XCV50E device. The
XCCACEM16_BG388.BSD,
and XCCACEM64.BSD files are available from the Xilinx
BSDL website under the software support pages at:
http://www.support.xilinx.com
XCCACEM32_BG388.BSD,
Figure 13:
System ACE MPM Boundary Scan Mode
1
2
3
TDI
TCK
TMS
TDO
XCV50E
TDI
RESET
A0-A21
1
DQ0-DQ15
OE
CE
WE
WP
RY/BY *
3
Boundary Scan
Register
4
XC18V01
TCK
TMS
TDO
TDI
System ACE MPM
TCK
TMS
TDO
*
*
2
ACC/WP on XCCACEM32; XCCACEM64 has separate WP and ACC pins.
*
3
RY/BY for XCCACEM16 and XCCACE32 only.
*
4
Boundary scan register is only conceptually depicted.
See the System ACE MPM BSDL file for accurate boundary-scan register information.
RESET
A0-A21 *
DQ0-DQ15
OE
CE
WE
ACC/WP *
RY/BY *
ACC
*2
Most XC18V01 signals remain inside
the MPM except a few status signals
shared with the XCV50E
XCV50E boundary scan can scan
most MPM signal pins for board test
ds087_14_091701
A21 for XCCACEM64 only; A20 for XCCACEM32 and XCCACEM64 only.
*
1
AMD Flash
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