參數(shù)資料
型號(hào)： XCCACEM16BG388I
廠商： XILINX INC
元件分類： 存儲(chǔ)器
英文描述： System ACE MPM Solution
中文描述： SPECIALTY MEMORY CIRCUIT, PBGA388
封裝： 35 X 35 MM, 2.70 MM HEIGHT, BGA-388
文件頁(yè)數(shù)： 7/29頁(yè)
文件大?。?/td> 283K
代理商： XCCACEM16BG388I
System ACE
MPM Solution
DS087 (v1.2) June 7, 2002
Advance Product Specification
www.xilinx.com
1-800-255-7778
7
R
System Control and Status Pins
Table 4
provides system control and status pins.
Power and Ground Pins
The System ACE MPM requires at least two power sup-
plies: 1.8V supplies power to the System ACE MPM config-
uration controller (an XCV50E) core; and 3.3V supplies
power to the Flash memory and configuration controller
PROM (an XC18V01). Additional power supplies may be
required for the output voltage compatibility pins:
FLASH_VCCO, CFG_VCCO, and CTRL_VCCO. See
Figure 4
and
Table 5
for a description of the System ACE
MPM power pins.
Table 4:
System Control and Status Pins
Pin Name
Pin Type
Description
FCM_ENABLE
Input
System ACE MPM controller enable. When this pin is held Low, all of the
System ACE MPM controller (XCV50E) pins tied to the Flash memory are
3-stated allowing external peripherals access to Flash memory without
contention.
FCMRESET
Input
System ACE MPM FPGA reset pin. The FCMRESET pin is connected to the
XCV50E PROGRAM pin. Applying a Low pulse to the FCMRESET resets the
XCV50E and forces the XCV50E to reconfigure itself from the XC18V01
PROM. (The XCV50E automatically configures itself from the XC18V01 PROM
at power-up.)
DEVRDY
Output
System ACE MPM FPGA DONE pin. The DEVRDY pin is connected to the
XCV50E DONE pin. When DEVRDY is High, the XCV50E is configured and
ready for operation.
SYSCLK
Input
SYSCLK is the system clock input for the System ACE MPM control logic.
SYSRESET
Input
Hold SYSRESET High for at least 10 SYSCLK cycles to reset the System ACE
MPM control logic. Upon release from the reset condition, the System ACE
MPM initiates the download procedure to the target FPGAs.
BITSTRSEL[2-0]
Input
The BITSTRSEL pins determine which of the eight configuration data streams
to download to the target FPGA.
STATUS[3-0]
Output
The STATUS pins indicate the status of the System ACE MPM control logic.
Figure 4:
Power Pins
DS087_04_090601
System ACE
MPM
CFG_VCCO
Configuration
Signals
VCCint1
VCCint2
FLASH_VCCO
CTRL_VCCO
Control
Signals
Slave-Serial
or
Slave-SelectMAP
Control
Circuits
BITSTRSEL[0-2]
SYSCLK
SYSRESET
1.8v
3.3v
CFG_VCCO
Compatible with
Target
FPGAs
CTRL_VCCO
Compatible with
Control Circuits
System Signals
Spartan-II
XILINX
Virtex-II
XILINX
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參數(shù)描述
XCCACEM16-BG388I 功能描述:SYS ACE MULTIPKG MODULE 16MBIT RoHS:否 類別:存儲(chǔ)卡，模塊 >> 存儲(chǔ)器 - 模塊 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 存儲(chǔ)器類型:SDRAM 存儲(chǔ)容量:1GB 速度:133MHz 特點(diǎn):- 封裝/外殼:168-DIMM
XCCACEM16SERIES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:System ACE MPM Solution
XCCACEM32BG388I 制造商:XILINX 制造商全稱:XILINX 功能描述:System ACE MPM Solution
XCCACEM32-BG388I 功能描述:SYS ACE MULTIPKG MODULE 32MBIT RoHS:否 類別:存儲(chǔ)卡，模塊 >> 存儲(chǔ)器 - 模塊 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 存儲(chǔ)器類型:SDRAM 存儲(chǔ)容量:1GB 速度:133MHz 特點(diǎn):- 封裝/外殼:168-DIMM
XCCACEM32SERIES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:System ACE MPM Solution
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