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參數(shù)資料
| 型號(hào)： | XC9536XL-4PC44C |
| 廠商： | XILINX INC |
| 元件分類： | PLD |
| 英文描述： | XC9536XL High PerformanceCPLD |
| 中文描述： | FLASH PLD, 4 ns, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大小： | 165K |
| 代理商： | XC9536XL-4PC44C |
Supported I/O Standards
The XC9536XV CPLD features both LVCMOS and LVTTL
I/O implementations. See
Table 1
for I/O standard voltages.
The LVTTL I/O standard is a general purpose EIA/JEDEC
standard for 3.3V applications that use an LVTTL input
buffer and Push-Pull output buffer. The LVCMOS2 standard
is used in 2.5V applications.
XC9500XV CPLDs are also 1.8V I/O compatible. The
X25TO18 setting is provided for generating 1.8V compatible
outputs from a CPLD normally operating in a 2.5V environ-
ment. The default I/O Standard for pads without IOSTAN-
DARD attributes is LVTTL for XC9500XV devices.
Figure 2:
XC9536XV Architecture
Function block outputs (indicated by the bold line) drive the I/O Blocks directly.
In-System Programming Controller
JTAG
Controller
I/O
Blocks
Function
Block 1
Macrocells
1 to 18
Macrocells
1 to 18
JTAG Port
3
54
I/O/GTS
I/O/GSR
I/O/GCK
I/O
I/O
I/O
I/O
2
1
I/O
I/O
I/O
I/O
3
DS053_02_041200
1
Function
Block 2
54
18
18
F
Table 1:
IOSTANDARD Options
IOSTANDARD
V
CCIO
3.3V
LVTTL
LVCMOS2
2.5V
X25TO18
1.8V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC9536XL-4PC44I | XC9536XL High PerformanceCPLD |
| XC9536XL-4VQ44I | XC9536XL High PerformanceCPLD |
| XC9536XL-4VQ64I | XC9536XL High PerformanceCPLD |
| XC9536XL-5CS48C | XC9536XL High PerformanceCPLD |
| XC9536XL-5CS48I | XC9536XL High PerformanceCPLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC9536XL-4PC44I | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC9536XL High PerformanceCPLD |
| XC9536XL-4VQ44C | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC9536XL High PerformanceCPLD |
| XC9536XL-4VQ44I | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC9536XL High PerformanceCPLD |
| XC9536XL-4VQ64C | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC9536XL High PerformanceCPLD |
| XC9536XL-4VQ64I | 制造商:XILINX 制造商全稱:XILINX 功能描述:XC9536XL High PerformanceCPLD |
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