參數(shù)資料
型號(hào): XC95288XV
廠商: Xilinx, Inc.
英文描述: High-Performance CPLD
中文描述: 高性能的CPLD
文件頁數(shù): 1/12頁
文件大?。?/td> 107K
代理商: XC95288XV
DS050 (v2.2) August 27, 2001
1
Advance Product Specification
1-800-255-7778
2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
288 macrocells with 6,400 usable gates
Available in small footprint packages
-
144-pin TQFP (117 user I/O pins)
-
208-pin PQFP (168 user I/O pins)
-
280-pin CSP (192 user I/O pins)
-
256-pin FBGA (192 user I/O pins)
Optimized for high-performance 2.5V systems
-
Low power operation
-
Multi-voltage operation
Advanced system features
-
In-system programmable
-
Four separate output banks
-
Superior pin-locking and routability with
FastCONNECT II switch matrix
-
Extra wide 54-input Function Blocks
-
Up to 90 product-terms per macrocell with
individual product-term allocation
-
Local clock inversion with three global and one
product-term clocks
-
Individual output enable per output pin
-
Input hysteresis on all user and boundary-scan pin
inputs
-
Bus-hold ciruitry on all user pin inputs
-
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
-
Endurance exceeding 10,000 program/erase
cycles
-
20 year data retention
-
ESD protection exceeding 2,000V
Description
The XC95288XV is a 2.5V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of 16
54V18 Function Blocks, providing 6,400 usable gates with
propagation delays of 5 ns.
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XV device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of ICC, the following equation may be
used:
ICC (mA) =
MCHP(0.36) + MCLP(0.23) + MC(0.005 mA/MHz) f
Where:
MCHP = Macrocells in high-performance (default) mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
This calculation is based on typical operating conditions
using a pattern of 16-bit up/down counters in each Function
Block with no output loading. The actual ICC value varies
with the design application and should be verified during
normal system operation.
Figure 1 shows the above estimation in a graphical form.
0
XC95288XV High-Performance
CPLD
DS050 (v2.2) August 27, 2001
05
Advance Product Specification
R
Figure 1: Typical ICC vs. Frequency for XC95288XV
Clock Frequency (MHz)
Typical
I
CC
(mA)
100
200
250
DS050_01_012501
200
250
300
350
400
450
50
150
100
0
120 MHz
High
Pe
rform
ance
200 MHz
Low
Po
we
r
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