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參數(shù)資料
| 型號(hào)： | XC95288-15HQ208C |
| 英文描述： | Flash Complex PLD |
| 中文描述： | 閃光復(fù)雜可編程邏輯器件 |
| 文件頁(yè)數(shù)： | 13/16頁(yè) |
| 文件大?。?/td> | 133K |
| 代理商： | XC95288-15HQ208C |
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R
September 15, 1999 (Version 5.0)
13
XC9500 In-System Programmable CPLD Family
5
Low Power Mode
All XC9500 devices offer a low-power mode for individual
macrocells or across all macrocells. This feature allows the
device power to be significantly reduced.
Each individual macrocell may be programmed in
low-power mode by the user. Performance-critical parts of
the application can remain in standard power mode, while
other parts of the application may be programmed for
low-power operation to reduce the overall power dissipa-
tion. Macrocells programmed for low-power mode incur
additional delay (t
LP
) in pin-to-pin combinatorial delay as
well as register setup time. Product term clock to output
and product term output enable delays are unaffected by
the macrocell power-setting.
Timing Model
The uniformity of the XC9500 architecture allows a simpli-
fied timing model for the entire device. The basic timing
model, shown in
Figure 14
, is valid for macrocell functions
that use the direct product terms only, with standard power
setting, and standard slew rate setting.
Table 4
shows how
each of the key timing parameters is affected by the prod-
uct term allocator (if needed), low-power setting, and
slew-limited setting.
The product term allocation time depends on the logic span
of the macrocell function, which is defined as one less than
the maximum number of allocators in the product term
path. If only direct product terms are used, then the logic
span is 0. The example in
Figure 6
shows that up to 15
product terms are available with a span of 1. In the case of
Figure 7
, the 18 product term function has a span of 2.
Detailed timing information may be derived from the full
timing model shown in
Figure 15
. The values and explana-
tions for each parameter are given in the individual device
data sheets.
Figure 13: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable
X5902
GND
V
CC
(a)
(b)
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| XC95288-20BG352I | Flash Complex PLD |
| XC95288-20HQ208I | Flash Complex PLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC9528815HQ208I | 制造商:XILINX 功能描述:* |
| XC95288-15HQ208I | 功能描述:IC CPLD 288 MCELL I-TEMP 208HQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:XC9500 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
| XC95288-20BG352C | 功能描述:IC CPLD 288 MCELL C-TEMP 352-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:XC9500 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
| XC95288-20BG352I | 功能描述:IC CPLD 288 MCELL I-TEMP 352-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:XC9500 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
| XC95288-20HQ208C | 功能描述:IC CPLD 288 MCELL C-TEMP 208HQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:XC9500 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
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