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參數(shù)資料
| 型號(hào)： | XC9101C30AKR |
| 廠商： | TOREX SEMICONDUCTOR LTD. |
| 英文描述： | PWM Controlled Step-Up DC/DC Controllers |
| 中文描述： | PWM控制升壓型DC / DC控制器 |
| 文件頁(yè)數(shù)： | 13/19頁(yè) |
| 文件大?。?/td> | 311K |
| 代理商： | XC9101C30AKR |
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5. FB Voltage and Cfb
With regard to the XC9101D series, the output voltage is set by attaching externally divided resistors. The output voltage is determined by the
equation shown below according to the values of Rfb1 and Rfb2. In general, the sum of Rfb1 and Rfb2 should be 1 MEG
or less.
V
OUT
= 0.9
×
(Rfb1 + Rfb2)/Rfb2
The value of Cfb (phase compensation capacitor) is approximated by the following equation according to the values of Rfb1 and fzfb. The value
of fzfb should be 10 kHz, as a general rule.
Cfb = 1/(2
× π ×
Rfb1
×
fzfb)
Example: When Rfb1 = 455 k
and Rfb2 = 100 k
: V
OUT
= 0.9
×
(455 k + 100 k)/100 k = 4.995 V
: Cfb = 1/(2
× π ×
455 k
×
10 k) = 34.98 pF
G
Application Notes
1. The XC9101 series are designed for use with an output ceramic capacitor. If, however, the potential difference between input and output is
too large, a ceramic capacitor may fail to absorb the resulting high switching energy and oscillation could occur on the output side. If the
input-output potential difference is large, connect an electrolytic capacitor in parallel to compensate for insufficient capacitance.
2.
The EXT pin of the XC9101 series is designed to minimize the through current that occurs in the internal circuitry. However, the gate drive
of external PMOS has a low impedance for the sake of speed. Therefore, if the input voltage is high and the bypass capacitor is attached
away from the IC, the charge/discharge current to the external PMOS may lead to unstable operations due to switching operation of the
EXT pin.
As a solution to this problem, place the bypass capacitor as close to the IC as possible, so that voltage variations at the V
IN
and V
SS
pins
caused by switching are minimized. If this is not effective, insert a resistor of several to several tens of ohms between the EXT pin and
PMOS gate. Remember that the insertion of a resistor slows down the switching speed and may result in reduced efficiency.
3.
A PNP transistor can be used in place of PMOS. If using a PNP transistor, insert a resistor (Rb) and capacitor (Cb) between the EXT pin
and the base of the PNP transistor in order to limit the base current without slowing the switching speed. Adjust Rb in a range of 500
to
1 k
according to the load and hFE of the transistor. Use a ceramic capacitor for Cb, complying with Cb
≤
1/(2
× π ×
Rb
×
Fosc
×
0.7), as a
rule.
4.
Although the C_CLK connection capacitance range is from 150 ~ 220pF, the most suitable value for maximum stability is around 180pF.
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