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參數(shù)資料
| 型號(hào)： | XC6VLX550T-2FFG1760E |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA VIRTEX 1760FCBGA |
| 產(chǎn)品培訓(xùn)模塊： | Virtex-6 FPGA Overview |
| 產(chǎn)品變化通告： | Virtex-6 FIFO Input Logic Reset 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 12 |
| 系列： | Virtex® 6 LXT |
| LAB/CLB數(shù)： | 42960 |
| 邏輯元件/單元數(shù)： | 549888 |
| RAM 位總計(jì)： | 23298048 |
| 輸入/輸出數(shù)： | 1200 |
| 電源電壓： | 0.95 V ~ 1.05 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 1760-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 1760-FCBGA |
| 其它名稱： | XC6VLX550T-2FFG1760I XC6VLX550T-2FFG1760I-ND |
Virtex-6 Family Overview
DS150 (v2.4) January 19, 2012
Product Specification
6
Block RAM
Every Virtex-6 FPGA has between 156 and 1064 dual-port block RAMs, each storing 36 Kbits. Each block RAM has two
completely independent ports that share nothing but the stored data.
Each memory access, read and write, is controlled by the clock. All inputs, data, address, clock enables, and write enables
are registered. Nothing happens without a clock. The input address is always clocked, retaining data until the next operation.
An optional output data pipeline register allows higher clock rates at the cost of an extra cycle of latency.
During a write operation, the data output can reflect either the previously stored data, the newly written data, or remain
unchanged.
Programmable Data Width
Each port can be configured as 32K × 1, 16K × 2, 8K × 4, 4K × 9 (or 8), 2K × 18 (or 16), 1K × 36 (or 32), or 512 x 72
(or 64). The two ports can have different aspect ratios, without any constraints.
Each block RAM can be divided into two completely independent 18 Kb block RAMs that can each be configured to any
aspect ratio from 16K x 1 to 512 x 36. Everything described previously for the full 36 Kb block RAM also applies to each
of the smaller 18 Kb block RAMs.
In 18 Kb block RAMs, only simple dual-port mode can provide data width of >36 bits. In this mode, one port is
dedicated to read and the other port is dedicated to write operation. In SDP mode one side (read or write) can be
variable while the other is fixed to 32/36 or 64/72. There is no read output during write. The dual-port 36 Kb RAM both
sides can be of variable width.
Two adjacent 36 Kb block RAMs can be configured as one cascaded 64K × 1 dual-port RAM without any additional
logic.
Error Detection and Correction
Each 64 bit-wide block RAM can generate, store, and utilize eight additional Hamming-code bits, and perform single-bit error
correction and double-bit error detection (ECC) during the read process. The ECC logic can also be used when writing to,
or reading from external 64/72-wide memories. This works in simple dual-port mode and does not support read-during-write.
FIFO Controller
The built-in FIFO controller for single-clock (synchronous) or dual-clock (asynchronous or multirate) operation increments
the internal addresses and provides four handshaking flags: full, empty, almost full, and almost empty. The almost full and
almost empty flags are freely programmable. Similar to the block RAM, the FIFO width and depth are programmable, but the
write and read ports always have identical width. First-word fall-through mode presents the first-written word on the data
output even before the first read operation. After the first word has been read, there is no difference between this mode and
the standard mode.
Digital Signal Processing—DSP48E1 Slice
DSP applications use many binary multipliers and accumulators, best implemented in dedicated DSP slices. All Virtex-6
FPGAs have many dedicated, full-custom, low-power DSP slices combining high speed with small size, while retaining
system design flexibility.
Each DSP48E1 slice fundamentally consists of a dedicated 25 × 18 bit two's complement multiplier and a 48-bit
accumulator, both capable of operating at 600 MHz. The multiplier can be dynamically bypassed, and two 48-bit inputs can
feed a single-instruction-multiple-data (SIMD) arithmetic unit (dual 24-bit add/subtract/accumulate or quad 12-bit
add/subtract/accumulate), or a logic unit that can generate any one of 10 different logic functions of the two operands.
The DSP48E1 includes an additional pre-adder, typically used in symmetrical filters. This new pre-adder improves
performance in densely packed designs and reduces the logic slice count by up to 50%.
The DSP48E1 slice provides extensive pipelining and extension capabilities that enhance speed and efficiency of many
applications, even beyond digital signal processing, such as wide dynamic bus shifters, memory address generators, wide
bus multiplexers, and memory-mapped I/O register files. The accumulator can also be used as a synchronous up/down
counter. The multiplier can perform logic functions (AND, OR) and barrel shifting.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| XC6VLX550T-L1FF1759C | 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 FAMILY 549888 CELLS 40NM (CMOS) TECHNOLOGY 1V - Trays 制造商:Xilinx 功能描述:IC FPGA 840 I/O 1759FCBGA |
| XC6VLX550T-L1FF1759I | 功能描述:IC FPGA VIRTEX-6LXT 1759FFBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex® 6 LXT 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XC6VLX550T-L1FF1760C | 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 FAMILY 549888 CELLS 40NM (CMOS) TECHNOLOGY 1V - Trays 制造商:Xilinx 功能描述:IC FPGA VIRTEX 6 550K 1760BGA 制造商:Xilinx 功能描述:IC FPGA 1200 I/O 1760FBGA |
| XC6VLX550T-L1FF1760I | 功能描述:IC FPGA VIRTEX-6LXT 1760FFBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex® 6 LXT 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XC6VLX550T-L1FFG1759C | 功能描述:IC FPGA VIRTEX 6 549K 1759FFGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex® 6 LXT 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
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