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| 型號： | XC68341FT16 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Integrated Processor Users Manual |
| 中文描述： | 綜合處理器用戶手冊 |
| 文件頁數(shù)： | 6/21頁 |
| 文件大?。?/td> | 134K |
| 代理商： | XC68341FT16 |
MOTOROLA
MC68341 USER’S MANUAL ADDENDUM
5
mination case #3. This can be done by asserting HALT and BERR either synchronously to the clock to directly
control which edge each is recognized on, or asynchronously with HALT asserted for time [spec 47A+spec
47B] ns before BERR to guarantee recognition on or before the same clock edge as BERR.
13. Active Negate on Bus Arbitration
The 68341 actively pulls up all tri-stateable bus pins other than the data bus before tristating them during bus
arbitration. This pullup function is not guaranteed to result in spec VOH levels before tristating, but will help
reduce rise time on these signals when using weak external bus pullups.
14. Additional Note on Bus Arbitration Priority
For the bus arbitration description beginning on page 3-49: The arbitration priority between possible bus mas-
ters for this device is external request via BR (highest priority), DMA, then CPU (lowest). The priority of DMA
channels 1 and 2 relative to each other is selected by their respective MAID levels which must be unique.
15. Additional Note on Bus Arbitration and Operand Coherency
For the bus arbitration description beginning on page 3-49: Each bus master maintains operand coherency
when a higher priority request is recognized. For example, a CPU write of a long-word operand to a byte port
results in a sequence of four bus cycles to complete the operand transfer - the CPU will not release the bus
until the completion of the fourth bus cycle. A single address DMA transfer is handled in a similar manner. For
a dual address DMA transfer, the read and write portions are handled as separate operands, allowing arbitra-
tion between the read and write bus cycles. Also, if different port sizes are specified in the DMA configuration
for the source and destination, arbitration can occur between each of the multiple operand accesses which
must be made to the smaller port for each operand access to the larger port. The RMC read/write sequences
for a TAS instruction is also indivisible to guarantee data coherency. Arbitration is allowed between each op-
erand transfer of a multi-operand operation such as a MOVEM instruction or exception stacking.
16. Additional Notes on RESET Interaction with Current Bus Cycle
Add to the Reset Operation description beginning page 3-55:
Hardware resets are held off until completion of the current operand transfer in order to maintain operand co-
herency. The processor resets at the end of the bus cycle in which the last portion of the operand is transferred,
or after the bus monitor has timed out. The bus monitor operates for this specific case whether it is enabled or
not, for the period of time that the BMT bits are set to.
The following reset sources reset all internal registers to their reset state: external, POR, software watchdog,
double bus fault, loss of clock. Execution of a RESET instruction resets the peripheral module registers with
the exception of the MCR registers. The MCR register in each module, the SIM41 registers, and the CPU state
are not affected by execution of a RESET instruction.
17. External Reset
On page 3-56, Figure 3-33, the RESET signal negates for two clocks between internal and external assertions,
not one. Note that RESET is not actively negated, and its rise time is dependent on the pullup resistor used.
18. Power-On Reset
On page 3-57, Figure 3-34. Power-Up Reset Timing Diagram: CLKOUT is not gated by VCO lock or other in-
ternal control signals, and can begin toggling as soon as VCC is high enough for the internal logic to begin
operating. For crystal mode and external clock with VCO mode, after the VCO frequency has reached an initial
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