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參數(shù)資料
| 型號(hào)： | XC6111A246 |
| 廠商： | TOREX SEMICONDUCTOR LTD. |
| 英文描述： | CMOS Voltage Detector |
| 中文描述： | CMOS電壓檢測(cè)器 |
| 文件頁數(shù)： | 15/26頁 |
| 文件大?。?/td> | 535K |
| 代理商： | XC6111A246 |
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15/26
XC6101 ~ XC6107, XC6111~ XC6117
Series
PIN NAME
LOGIC
H
L
H
L
H
L
L
→
H
H
→
L
CONDITIONS
V
IN
>V
DF
+V
HYS
V
IN
<V
DF
MRB>1.40V
MRB<0.35V
V
IN
MRB
When keeping W
D
>V
WDH
more than T
WD
When keeping W
D
<V
WDL
more than T
WD
V
WDL
→
V
WDH
, T
WDIN
>300nsec
V
WDH
→
V
WDH
, T
WDIN
>300nsec
WD
V
IN
H
H
H
H
H
H
L
MRB
WD
H
L
Open
L
→
H
H
→
L
RESETB (*2)
Repeat detect and release (H
→
L
→
H)
H or Open
H
L
*1
L
V
IN
H
H
H
H
H
H
L
MRB
WD
H
L
Open
L
→
H
H
→
L
RESETB (*3)
Repeat detect and release (L
→
H
→
L)
H or Open
L
L
*1
H
V
IN
H
H
H
H
H
H
L
WD
H
L
Open
L
→
H
H
→
L
RESETB (*2)
RESET (*3)
Repeat detect and release (H
→
L
→
H)
Repeat detect and release (L
→
H
→
L)
H
L
*1
L
H
V
IN
H
H
L
MRB
H or Open
RESETB (*2)
H
RESET (*3)
L
L
L
H
■
PIN LOGIC CONDITIONS
NOTE:
*1: If only “V
DF
” is indicated, it represents both V
DFL
(low when
detected) and V
DFH
(high when detected).
*2: For the details of each parameter, please see the electrical
characteristics.
V
DF
: Detect Voltage
V
HYS
: Hysteresis Range
V
WDH
: WD High Level Voltage
V
WDL:
WD Low Level Voltage
T
WDIN
: WD Pulse Width
T
WD
: WD Timeout Period
■
FUNCTION CHART
●
XC6103/XC61113 Series
●
XC6104/XC61114, XC6105/XC6115 Series
●
XC6106/XC61116, XC6107/XC6117 Series
●
XC6101/XC61111, XC6102/6112 Series
*1: Including all logic of WD (WD=H, L, L
→
H, H
→
L, OPEN).
*2: When the RESETB is High, the circuit is in the release state.
When the RESETB is Low, the circuit is in the detection state.
*3: When the RESET is High, the circuit is in the release state.
When the RESET is Low, the circuit is in the detection state.
*4: V
IN
=L and MRB=H can not be combined for the rated input voltage of the MRB pin is Vss-0.3V to V
IN
+0.3V.
*5: The RESET/RESETB pin becomes indefinite operation while 0.35V<MRB<1.4V.
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