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參數(shù)資料
型號: XC5VLX50-1FFG676I
廠商: Xilinx Inc
文件頁數(shù): 68/91頁
文件大小: 0K
描述: IC FPGA VIRTEX-5 50K 676-FBGA
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-5 LX
LAB/CLB數(shù): 3600
邏輯元件/單元數(shù): 46080
RAM 位總計: 1769472
輸入/輸出數(shù): 440
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 676-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 676-FCBGA(27x27)
配用: 568-5088-ND - BOARD DEMO DAC1408D750
HW-V5-ML561-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML550-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML521-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5GBE-DK-UNI-G-ND - KIT DEV V5 LXT GIGABIT ETHERNET
122-1508-ND - EVALUATION PLATFORM VIRTEX-5
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
70
TPSFD/ TPHFD
Full Delay (Legacy Delay or Default Delay)
Global Clock and IFF(2) without DCM or PLL
XC5VTX150T
N/A
2.35
–0.82
2.59
–0.82
ns
XC5VTX240T
N/A
2.59
–0.85
2.87
–0.85
ns
XC5VFX30T
2.05
–0.27
2.25
–0.27
2.57
–0.27
ns
XC5VFX70T
1.85
–0.30
2.06
–0.30
2.35
–0.30
ns
XC5VFX100T
2.20
–0.42
2.38
–0.42
2.66
–0.42
ns
XC5VFX130T
2.33
–0.55
2.59
–0.54
2.95
–0.54
ns
XC5VFX200T
N/A
2.52
–0.43
2.81
–0.43
ns
Notes:
1.
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
2.
IFF = Input Flip-Flop or Latch
3.
A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0"
is listed, there is no positive hold time.
Table 91: Global Clock Setup and Hold Without DCM or PLL (Cont’d)
Symbol
Description
Device
Speed Grade
Units
-3
-2
-1
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