參數(shù)資料
型號(hào): XC5VLX50-1FFG324I
廠商: Xilinx Inc
文件頁數(shù): 86/91頁
文件大小: 0K
描述: IC FPGA VIRTEX-5 50K 324FBGA
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-5 LX
LAB/CLB數(shù): 3600
邏輯元件/單元數(shù): 46080
RAM 位總計(jì): 1769472
輸入/輸出數(shù): 220
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 324-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 324-FCBGA(19x19)
配用: 568-5088-ND - BOARD DEMO DAC1408D750
HW-V5-ML561-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML550-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML521-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-AFX-FF324-500-G-ND - BOARD DEV VIRTEX 5 FF324
HW-V5GBE-DK-UNI-G-ND - KIT DEV V5 LXT GIGABIT ETHERNET
122-1508-ND - EVALUATION PLATFORM VIRTEX-5
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
87
02/02/07
3.0
Added XC5VSX35T, XC5VSX50T, and SX5VSX95T devices to appropriate tables.
Revised the IRPU values in Table 3, page 2.
Revised the ICCAUXQ values in Table 4, page 3.
Added values to Table 5, page 6.
Minor added notes and changed descriptions in Table 25, page 13 and Table 26, page 13.
Revised the SFI-4.1 (SDR LVDS Interface) -1 values in Table 53, page 29.
Revised gain error, bipolar gain error, and event conversion time in Table51, page26
Changed the design software version that matches this data sheet above Table 54 on page 30.
In Switching Characteristics, the following values are revised:
LVCMOS25, Fast, 12 mA in Table 56, page 32.
Setup and Hold and TICKQ in Table 60, page 40.
Sequential delay values in Table 63, page 43.
TCXB, TCEO, and TDICK in Table 65, page 44.
TRCKO_DO, TRCKO_POINTERS, TRCKO_ECCR, TRCKO_ECC, TRCCK_ADDR, TRDCK_DI, TRDCK_DI_ECC,
TRCCK_WREN, and TRCO_FLAGS in Table 68, page 47.
TDSPDCK_CC, TDSPCCK_{RSTAA, RSTBB}, TDSPCKO_{PP, CRYOUTP}, FMAX_MULT_NOMREG and
FMAX_MULT_NOMREG_PATDET in Table 69, page 48.
TBCCKO_O, and TBGCKO_O in Table 71, page 53.
TBUFIOCKO_O and FMAX in Table 72, page 53.
TBRCKO_O and TBRCKO_O_BYP in Table 73, page 54.
Parameters in Table 74, page 55 including notes.
Revised values in Table 84, Table 85, and Table 86.
Clarified description in Table 91, page 69.
Revised values in Table 91, Table 92, and Table 93.
Removed duplicate TBUFR_MAX_FREQ and TBUFIO_MAX_FREQ from Table 98.
Revised values in Table 101, page 85.
Date
Version
Revision
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XC5VLX50-1FF324I IC FPGA VIRTEX-5 50K 324FBGA
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