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參數(shù)資料
| 型號： | XC5VLX30T-3FFG665C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA VIRTEX-5LX 30K 665-FCBGA |
| 產(chǎn)品變化通告： | Step Intro and Pkg Change 11/March/2008 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Virtex®-5 LXT |
| LAB/CLB數(shù)： | 2400 |
| 邏輯元件/單元數(shù)： | 30720 |
| RAM 位總計： | 1327104 |
| 輸入/輸出數(shù)： | 360 |
| 電源電壓： | 0.95 V ~ 1.05 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 665-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 665-FCBGA |
| 配用： | 568-5088-ND - BOARD DEMO DAC1408D750 |
Virtex-5 Family Overview
4
DS100 (v5.0) February 6, 2009
Product Specification
R
Digitally Controlled Impedance (DCI)
Active I/O Termination
Optional series or parallel termination
Temperature and voltage compensation
Makes board layout much easier
Reduces resistors
Places termination in the ideal location, at the signal
source or destination
Configuration
Support for platform Flash, standard SPI Flash, or
standard parallel NOR Flash configuration
Bitstream support with dedicated fallback
reconfiguration logic
256-bit AES bitstream decryption provides intellectual
property security and prevents design copying
Improved bitstream error detection/correction capability
Auto bus width detection capability
Partial Reconfiguration via ICAP port
Advanced Flip-Chip Packaging
Pre-engineered packaging technology for proven
superior signal integrity
Minimized inductive loops from signal to return
Optimal signal-to-PWR/GND ratios
Reduces SSO induced noise by up to 7x
Pb-Free and standard packages
System Monitor
On-Chip temperature measurement (±4°C)
On-Chip power supply measurement (±1%)
Easy to use, self-contained
No design required for basic operation
Autonomous monitoring of all on-chip sensors
User programmable alarm thresholds for on-chip
sensors
User accessible 10-bit 200kSPS ADC
Automatic calibration of offset and gain error
DNL = ±0.9 LSBs maximum
Up to 17 external analog input channels supported
0V to 1V input range
Monitor external sensors e.g., voltage, temperature
General purpose analog inputs
Full access from fabric or JTAG TAP to System Monitor
Fully operational prior to FPGA configuration and
during device power down (access via JTAG TAP only)
65-nm Copper CMOS Process
1.0V Core Voltage
12-layer metal provides maximum routing capability
and accommodates hard-IP immersion
Triple-oxide technology for proven reduced static power
consumption
System Blocks Specific to the LXT, SXT, TXT, and FXT Devices
Integrated Endpoint Block for PCI Express
Compliance
Works in conjunction with RocketIO GTP transceivers
(LXT and SXT) and GTX transceivers (TXT and FXT)
to deliver full PCI Express Endpoint functionality with
minimal FPGA logic utilization.
Compliant with the PCI Express Base Specification 1.1
PCI Express Endpoint block or Legacy PCI Express
Endpoint block
x8, x4, or x1 lane width
Power management support
Block RAMs used for buffering
Fully buffered transmit and receive
Management interface to access PCI Express
configuration space and internal configuration
Supports the full range of maximum payload sizes
Up to 6 x 32 bit or 3 x 64 bit BARs (or a combination of
32 bit and 64 bit)
Tri-Mode Ethernet Media Access Controller
Designed to the IEEE 802.3-2002 specification
Operates at 10, 100, and 1,000 Mb/s
Supports tri-mode auto-negotiation
Receive address filter (5 address entries)
Fully monolithic 1000Base-X solution with RocketIO
GTP transceivers
Supports multiple external PHY connections (RGMII,
GMII, etc.) interfaces through soft logic and SelectIO
resources
Supports connection to external PHY device through
SGMII using soft logic and RocketIO GTP transceivers
Receive and transmit statistics available through
separate interface
Separate host and client interfaces
Support for jumbo frames
Support for VLAN
Flexible, user-configurable host interface
Supports IEEE 802.3ah-2004 unidirectional mode
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| XC5VLX30T-X1FF323C | 制造商:Xilinx 功能描述: |
| XC5VLX30T-X1FF665C | 制造商:Xilinx 功能描述: |
| XC5VLX30T-X1FFG323C | 制造商:Xilinx 功能描述: |
| XC5VLX30T-X1FFG665C | 制造商:Xilinx 功能描述: |
| XC5VLX30-X1FF324C | 制造商:Xilinx 功能描述: |
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