參數(shù)資料
型號(hào)： XC5VLX30-2FFG324I
廠商： Xilinx Inc
文件頁數(shù)： 11/91頁
文件大?。?/td> 0K
描述： IC FPGA VIRTEX-5 30K 324FBGA
標(biāo)準(zhǔn)包裝： 1
系列： Virtex®-5 LX
LAB/CLB數(shù)： 2400
邏輯元件/單元數(shù)： 30720
RAM 位總計(jì)： 1179648
輸入/輸出數(shù)： 220
電源電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 324-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 324-FCBGA（19x19）
配用： 568-5088-ND - BOARD DEMO DAC1408D750
HW-AFX-FF324-500-G-ND - BOARD DEV VIRTEX 5 FF324
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
19
GTX_DUAL Tile Specifications
GTX_DUAL Tile DC Characteristics
Table 36: Absolute Maximum Ratings for GTX_DUAL Tiles
Symbol
Description
Units
MGTAVCCPLL
Analog supply voltage for the GTX_DUAL shared PLL relative to GND
–0.5 to 1.1
V
MGTAVTTTX
Analog supply voltage for the GTX_DUAL transmitters relative to GND
–0.5 to 1.32
V
MGTAVTTRX
Analog supply voltage for the GTX_DUAL receivers relative to GND
–0.5 to 1.32
V
MGTAVCC
Analog supply voltage for the GTX_DUAL common circuits relative to GND
–0.5 to 1.1
V
MGTAVTTRXC
Analog supply voltage for the resistor calibration circuit of the GTX_DUAL
column
–0.5 to 1.32
V
Notes:
1.
Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Table 37: Recommended Operating Conditions for GTX_DUAL Tiles(1)(2)
Symbol
Description
Min
Max
Units
MGTAVCCPLL(1)
Analog supply voltage for the GTX_DUAL shared PLL relative to GND
0.95
1.05
V
MGTAVTTTX(1)
Analog supply voltage for the GTX_DUAL transmitters relative to GND
1.14
1.26
V
MGTAVTTRX(1)
Analog supply voltage for the GTX_DUAL receivers relative to GND
1.14
1.26
V
MGTAVCC(1)
Analog supply voltage for the GTX_DUAL common circuits relative to GND
0.95
1.05
V
MGTAVTTRXC(1) Analog supply voltage for the resistor calibration circuit of the GTX_DUAL
column
1.14
1.26
V
Notes:
1.
Each voltage listed requires the filter circuit described in UG198: Virtex-5 FPGA RocketIO GTX Transceiver User Guide.
2.
Voltages are specified for the temperature range of TJ = –40°C to +100°C.
Table 38: DC Characteristics Over Recommended Operating Conditions for GTX_DUAL Tiles(1)
Symbol
Description
Min
Typ
Max
Units
IMGTAVTTTX
GTX_DUAL tile transmitter termination supply current(2)
43.3
86.3
mA
IMGTAVCCPLL
GTX_DUAL tile shared PLL supply current
38.0
99.4
mA
IMGTAVTTRXC
GTX_DUAL tile resistor termination calibration supply current
0.1
0.5
mA
IMGTAVTTRX
GTX_DUAL tile receiver termination supply current(3)
40.3
56.5
mA
IMGTAVCC
GTX_DUAL tile internal analog supply current
80.5
179.5
mA
MGTRREF
Precision reference resistor for internal calibration termination
59.0 ± 1% tolerance
Ω
Notes:
1.
Typical values are specified at nominal voltage, 25°C, with a 3.2 Gb/s line rate.
2.
ICC numbers are given per GTX_DUAL tile with both GTX transceivers operating with default settings.
3.
AC coupled TX/RX link.
4.
Values for currents other than the values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER
Analyzer (XPA) tools.
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