參數(shù)資料
型號(hào): XC5VLX110-2FFG1760C
廠商: Xilinx Inc
文件頁數(shù): 49/91頁
文件大?。?/td> 0K
描述: IC FPGA VIRTEX-5 110K 1760FBGA
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-5 LX
LAB/CLB數(shù): 8640
邏輯元件/單元數(shù): 110592
RAM 位總計(jì): 4718592
輸入/輸出數(shù): 800
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 1760-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1760-FCBGA
配用: 568-5088-ND - BOARD DEMO DAC1408D750
HW-V5-ML523-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-AFX-FF1760-500-G-ND - BOARD DEV VIRTEX 5 FF1760
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
53
Clock Buffers and Networks
Table 71: Global Clock Switching Characteristics (Including BUFGCTRL)
Symbol
Description
Devices
Speed Grade
Units
-3
-2
-1
TBCCCK_CE/TBCCKC_CE(1)
CE pins Setup/Hold
All
0.27
0.00
0.27
0.00
0.31
0.00
ns
TBCCCK_S/TBCCKC_S(1)
S pins Setup/Hold
All
0.27
0.00
0.27
0.00
0.31
0.00
ns
TBCCKO_O(2)
BUFGCTRL delay from
I0/I1 to O
LX20T
N/A
0.24
0.30
ns
LX30, LX30T, LX50, LX50T,
LX85, LX85T, LX110, LX110T,
SX35T, SX50T, FX70T,
FX100T, and FX130T
0.19
0.22
0.25
ns
FX30T
0.23
0.25
ns
LX155 and LX155T
0.12
0.14
0.30
ns
LX220, LX220T, LX330,
LX330T, SX95T, SX240T,
TX150T, TX240T, and FX200T
N/A
0.22
0.25
ns
Maximum Frequency
FMAX
Global clock tree (BUFG)
LX20T
N/A
667
600
MHz
LX30, LX30T, LX50, LX50T,
LX85, LX85T, LX110, LX110T,
SX35T, SX50T, FX30T, and
FX70T
710
667
600
MHz
LX155, LX155T, and FX100T
650
600
550
MHz
FX130T
550
500
450
MHz
LX220, LX220T, LX330,
LX330T, SX95T, SX240T,
TX150T, TX240T, and FX200T
N/A
500
450
MHz
Notes:
1.
TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
parameters do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold times
are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between
clocks.
2.
TBGCKO_O (BUFG delay from I0 to O) values are the same as TBCCKO_O values.
Table 72: Input/Output Clock Switching Characteristics (BUFIO)
Symbol
Description
Speed Grade
Units
-3
-2
-1
TBUFIOCKO_O
Clock to out delay from I to O
1.08
1.16
1.29
ns
Maximum Frequency
FMAX
I/O clock tree (BUFIO)
710
644
MHz
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