參數(shù)資料
型號(hào): XC5VLX110-2FF1153C
廠商: Xilinx Inc
文件頁(yè)數(shù): 47/91頁(yè)
文件大?。?/td> 0K
描述: IC FPGA VIRTEX-5 110K 1153FBGA
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-5 LX
LAB/CLB數(shù): 8640
邏輯元件/單元數(shù): 110592
RAM 位總計(jì): 4718592
輸入/輸出數(shù): 800
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 1153-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1153-FCBGA(35x35)
配用: 568-5088-ND - BOARD DEMO DAC1408D750
HW-V5-ML523-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-AFX-FF1153-500-G-ND - BOARD DEV VIRTEX 5 FF1153
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
51
Configuration Switching Characteristics
Table 70: Configuration Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-2
-1
Power-up Timing Characteristics
TPL
Program Latency
3
ms, Max
TPOR
Power-on-Reset
10
50
10
50
10
50
ms, Min/Max
TICCK
CCLK (output) delay
400
ns, Min
TPROGRAM
Program Pulse Width
250
ns, Min
Master/Slave Serial Mode Programming Switching(1)
TDCCK/TCCKD
DIN Setup/Hold, slave mode
4.0
0.0
4.0
0.0
4.0
0.0
ns, Min
TDSCCK/TSCCKD
DIN Setup/Hold, master mode
4.0
0.0
4.0
0.0
4.0
0.0
ns, Min
TCCO
DOUT
7.5
ns, Max
FMCCK
Maximum Frequency, master mode with
respect to nominal CCLK.
100
MHz,
Max
FMCCKTOL
Frequency Tolerance, master mode with
respect to nominal CCLK.
±50
%
FMSCCK
Slave mode external CCLK
100
MHz
SelectMAP Mode Programming Switching(1)
TSMDCCK/TSMCCKD
SelectMAP Data Setup/Hold
3.0
0.5
3.0
0.5
3.0
0.5
ns, Min
TSMCSCCK/TSMCCKCS
CS_B Setup/Hold
3.0
0.5
3.0
0.5
3.0
0.5
ns, Min
TSMCCKW/TSMWCCK
RDWR_B Setup/Hold
8.0
0.5
8.0
0.5
8.0
0.5
ns, Min
TSMCKCSO
CSO_B clock to out
(330
Ω pull-up resistor required)
10
ns, Min
TSMCO
CCLK to DATA out in readback
9.0
ns, Max
TSMCKBY
CCLK to BUSY out in readback
7.5
ns, Max
FSMCCK
Maximum Frequency with respect to nominal
CCLK.
100
MHz, Max
FRBCCK
Maximum Readback Frequency with respect
to nominal CCLK
60
MHz, Max
FMCCKTOL
Frequency Tolerance with respect to nominal
CCLK.
±50
%
Boundary-Scan Port Timing Specifications
TTAPTCK
TMS and TDI Setup time before TCK
1.0
ns, Min
TTCKTAP
TMS and TDI Hold time after TCK
2.0
ns, Min
TTCKTDO
TCK falling edge to TDO output valid
6
ns, Max
FTCK
Maximum configuration TCK clock frequency
66
MHz, Max
FTCKB
Maximum boundary-scan TCK clock
frequency
66
MHz, Max
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XC5VLX110-2FF1153I 功能描述:IC FPGA VIRTEX-5 110K 1153FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:Virtex®-5 LX 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA(34.55x34.55)
XC5VLX110-2FF1760C 功能描述:IC FPGA VIRTEX-5 110K 1760FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:Virtex®-5 LX 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA(34.55x34.55)
XC5VLX110-2FF1760I 功能描述:IC FPGA VIRTEX-5 110K 1760FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:Virtex®-5 LX 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA(34.55x34.55)
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