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參數(shù)資料
| 型號： | XC5VFX130T-1FFG1738C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA VIRTEX-5FX 130K 1738FBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Virtex®-5 FXT |
| LAB/CLB數(shù)： | 10240 |
| 邏輯元件/單元數(shù)： | 131072 |
| RAM 位總計： | 10985472 |
| 輸入/輸出數(shù)： | 840 |
| 電源電壓： | 0.95 V ~ 1.05 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 1738-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 1738-FCBGA |
| 配用： | 568-5088-ND - BOARD DEMO DAC1408D750 HW-V5-ML510-G-ND - BOARD EVAL FOR VIRTEX-5 ML510 |
Virtex-5 Family Overview
DS100 (v5.0) February 6, 2009
Product Specification
3
R
Virtex-5 FPGA Logic
On average, one to two speed grade improvement over
Virtex-4 devices
Cascadable 32-bit variable shift registers or 64-bit
distributed memory capability
Superior routing architecture with enhanced diagonal
routing supports block-to-block connectivity with
minimal hops
Up to 330,000 logic cells including:
Up to 207,360 internal fabric flip-flops with clock enable
(XC5VLX330)
Up to 207,360 real 6-input look-up tables (LUTs) with
greater than 13 million total LUT bits
Two outputs for dual 5-LUT mode gives enhanced
utilization
Logic expanding multiplexers and I/O registers
550 MHz Clock Technology
Up to six Clock Management Tiles (CMTs)
Each CMT contains two DCMs and one PLL—up to
eighteen total clock generators
Flexible DCM-to-PLL or PLL-to-DCM cascade
Precision clock deskew and phase shift
Flexible frequency synthesis
Multiple operating modes to ease performance trade-off
decisions
Improved maximum input/output frequency
Fine-grained phase shifting resolution
Input jitter filtering
Low-power operation
Wide phase shift range
Differential clock tree structure for optimized low-jitter
clocking and precise duty cycle
32 global clock networks
Regional, I/O, and local clocks in addition to global
clocks
SelectIO Technology
Up to 1,200 user I/Os
Wide selection of I/O standards from 1.2V to 3.3V
Extremely high-performance
Up to 800 Mb/s HSTL and SSTL
(on all single-ended I/Os)
Up to 1.25 Gb/s LVDS (on all differential I/O pairs)
True differential termination on-chip
Same edge capture at input and output I/Os
Extensive memory interface support
550 MHz Integrated Block Memory
Up to 16.4 Mbits of integrated block memory
36-Kbit blocks with optional dual 18-Kbit mode
True dual-port RAM cells
Independent port width selection (x1 to x72)
Up to x36 total per port for true dual port operation
Up to x72 total per port for simple dual port operation
(one Read port and one Write port)
Memory bits plus parity/sideband memory support for
x9, x18, x36, and x72 widths
Configurations from 32K x 1 to 512 x 72
(8K x 4 to 512 x 72 for FIFO operation)
Multirate FIFO support logic
Full and Empty flag with fully programmable Almost Full
and Almost Empty flags
Synchronous FIFO support without Flag uncertainty
Optional pipeline stages for higher performance
Byte-write capability
Dedicated cascade routing to form 64K x 1 memory
without using FPGA routing
Integrated optional ECC for high-reliability memory
requirements
Special reduced-power design for 18 Kbit (and below)
operation
550 MHz DSP48E Slices
25 x 18 two’s complement multiplication
Optional pipeline stages for enhanced performance
Optional 48-bit accumulator for multiply accumulate
(MACC) operation with optional accumulator cascade
to 96-bits
Integrated adder for complex-multiply or multiply-add
operation
Optional bitwise logical operation modes
Independent C registers per slice
Fully cascadable in a DSP column without external
routing resources
ChipSync Source-Synchronous
Interfacing Logic
Works in conjunction with SelectIO technology to
simplify source-synchronous interfaces
Per-bit deskew capability built into all I/O blocks
(variable delay line on all inputs and outputs)
Dedicated I/O and regional clocking resources (pins
and trees)
Built-in data serializer/deserializer logic with
corresponding clock divider support in all I/O
Networking/telecommunication interfaces up to
1.25 Gb/s per I/O
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC5VFX130T-1FFG1738CES | 制造商:Xilinx 功能描述: |
| XC5VFX130T-1FFG1738I | 功能描述:IC FPGA VIRTEX-5FX 130K 1738FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-5 FXT 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XC5VFX130T-2FF1738C | 制造商:Xilinx 功能描述:FPGA VIRTEX-5 65NM 1V 1738FCBGA - Trays 制造商:Xilinx 功能描述:IC FPGA 840 I/O 1738FCBGA 制造商:Xilinx 功能描述:IC FPGA VIRTEX5FX 130K 1738BGA |
| XC5VFX130T-2FF1738I | 功能描述:IC FPGA VIRTEX-5FXT 1738FFBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-5 FXT 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XC5VFX130T-2FFG1738C | 功能描述:IC FPGA VIRTEX-5FX 130K 1738FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-5 FXT 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
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