參數(shù)資料
型號(hào): XC5210-5PQ160I
英文描述: Field Programmable Gate Array (FPGA)
中文描述: 現(xiàn)場(chǎng)可編程門(mén)陣列(FPGA)
文件頁(yè)數(shù): 44/73頁(yè)
文件大?。?/td> 598K
代理商: XC5210-5PQ160I
R
XC5200 Series Field Programmable Gate Arrays
7-126
November 5, 1998 (Version 5.2)
XC5200 Program Readback Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements.
The following guidelines reflect worst-case values over the recommended operating conditions.
Note 1: Timing parameters apply to all speed grades.
Note 2: rdbk.TRIG is High prior to Finished, Finished will trigger the first Readback
Description
rdbk.TRIG setup to initiate and abort Readback
rdbk.TRIG hold to initiate and abort Readback
rdbk.DATA delay
rdbk.RIP delay
High time
Low time
Symbol
T
RTRC
T
RCRT
T
RCRD
T
RCRR
T
RCH
T
RCL
Min
200
50
-
-
250
250
Max
-
-
250
250
500
500
Units
ns
ns
ns
ns
ns
ns
rdbk.TRIG
1
2
7
6
5
4
rdclk.1
RTRC
T
RCRT
T
2
RCL
T
4
RCRR
T
6
RCH
T
5
RCRD
T
7
DUMMY
DUMMY
rdbk.DATA
rdbk.RIP
rdclk.I
rdbk.TRIG
Finished
Internal Net
VALID
RTL
T
3
X1790
VALID
1
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