參數(shù)資料
型號： XC5202-6PG156C
廠商： XILINX INC
元件分類： FPGA
英文描述： Field Programmable Gate Arrays
中文描述： FPGA, 64 CLBS, 2000 GATES, 83 MHz, CPGA156
封裝： CERAMIC, PGA-156
文件頁數(shù)： 42/73頁
文件大?。?/td> 598K
代理商： XC5202-6PG156C
R
XC5200 Series Field Programmable Gate Arrays
7-124
November 5, 1998 (Version 5.2)
Notes
: 1. A shaded table cell represents a 20-k
to 100-k
pull-up resistor before and during configuration.
2. (I) represents an input (O) represents an output.
3. INIT is an open-drain output during configuration.
Table 13.
Pin Functions During Configuration
CONFIGURATION MODE:
<M2:M1:M0>
USER
OPERATION
SLAVE
<1:1:1>
MASTER-SER
<0:0:0>
SYN.PERIPH
<0:1:1>
ASYN.PERIPH
<1:0:1>
MASTER-HIGH
<1:1:0>
A16
A17
TDI
TCK
TMS
MASTER-LOW
<1:0:0>
A16
A17
TDI
TCK
TMS
EXPRESS
<0:1:0>
GCK1-I/O
I/O
TDI-I/O
TCK-I/O
TMS-I/O
I/O
I/O
I/O
I/O
GCK2-I/O
I/O
I/O
I/O
I/O
DONE
PROGRAM
I/O
GCK3-I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CCLK (I)
TDO-I/O
I/O
GCK4-I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ALL OTHERS
TDI
TCK
TMS
TDI
TCK
TMS
TDI
TCK
TMS
TDI
TCK
TMS
TDI
TCK
TMS
M1 (HIGH) (I)
M0 (HIGH) (I)
M2 (HIGH) (I)
M1 (LOW) (I)
M0 (LOW) (I)
M2 (LOW) (I)
M1 (HIGH) (I)
M0 (HIGH) (I)
M2 (LOW) (I)
M1 (LOW) (I)
M0 (HIGH) (I)
M2 (HIGH) (I)
M1 (HIGH) (I)
M0 (LOW) (I)
M2 (HIGH) (I)
M1 (LOW) (I)
M0 (LOW) (I)
M2 (HIGH) (I)
M1 (HIGH) (I)
M0 (LOW) (I)
M2 (LOW) (I)
HDC (HIGH)
LDC (LOW)
INIT-ERROR
HDC (HIGH)
LDC (LOW)
INIT-ERROR
HDC (HIGH)
LDC (LOW)
INIT-ERROR
HDC (HIGH)
LDC (LOW)
INIT-ERROR
HDC (HIGH)
LDC (LOW)
INIT-ERROR
HDC (HIGH)
LDC (LOW)
INIT-ERROR
HDC (HIGH)
LDC (LOW)
INIT-ERROR
DONE
DONE
DONE
DONE
DONE
DONE
DONE
PROGRAM (I)
PROGRAM (I)
PROGRAM (I)
DATA 7 (I)
PROGRAM (I)
DATA 7 (I)
PROGRAM (I)
DATA 7 (I)
PROGRAM (I)
DATA 7 (I)
PROGRAM (I)
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 6 (I)
DATA 5 (I)
CSO (I)
DATA 4 (I)
DATA 3 (I)
RS (I)
DATA 2 (I)
DATA 1 (I)
RDY/BUSY
DATA 0 (I)
DOUT
CCLK (O)
TDO
WS (I)
DATA 6 (I)
DATA 5 (I)
DATA 6 (I)
DATA 5 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 4 (I)
DATA 3 (I)
DATA 4 (I)
DATA 3 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
RDY/BUSY
DATA 0 (I)
DOUT
CCLK (I)
TDO
DATA 2 (I)
DATA 1 (I)
RCLK
DATA 0 (I)
DOUT
CCLK (O)
TDO
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
DATA 2 (I)
DATA 1 (I)
RCLK
DATA 0 (I)
DOUT
CCLK (O)
TDO
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
DATA 2 (I)
DATA 1 (I)
DIN (I)
DOUT
CCLK (I)
TDO
DIN (I)
DOUT
CCLK (O)
TDO
DATA 0 (I)
DOUT
CCLK (I)
TDO
CS1 (I)
CS1 (I)
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