• 參數(shù)資料
    型號(hào)： XC5202-5PQ160C
    廠商： Xilinx, Inc.
    英文描述： Field Programmable Gate Arrays
    中文描述： 現(xiàn)場(chǎng)可編程門陣列
    文件頁(yè)數(shù)： 4/73頁(yè)
    文件大小： 598K
    代理商： XC5202-5PQ160C
    R
    XC5200 Series Field Programmable Gate Arrays
    7-86
    November 5, 1998 (Version 5.2)
    The XC5200 CLB consists of four LCs, as shown in
    Figure 4
    . Each CLB has 20 independent inputs and 12
    independent outputs. The top and bottom pairs of LCs can
    be configured to implement 5-input functions. The chal-
    lenge of FPGA implementation software has always been
    to maximize the usage of logic resources. The XC5200
    family addresses this issue by surrounding each CLB with
    two types of local interconnect — the Local Interconnect
    Matrix (LIM) and direct connects. These two interconnect
    resources, combined with the CLB, form the VersaBlock,
    represented in
    Figure 2
    .
    The LIM provides 100% connectivity of the inputs and out-
    puts of each LC in a given CLB. The benefit of the LIM is
    that no general routing resources are required to connect
    feedback paths within a CLB. The LIM connects to the
    GRM via 24 bidirectional nodes.
    The direct connects allow immediate connections to neigh-
    boring CLBs, once again without using any of the general
    interconnect. These two layers of local routing resource
    improve the granularity of the architecture, effectively mak-
    ing the XC5200 family a “sea of logic cells.” Each
    Versa-Block has four 3-state buffers that share a common
    enable line and directly drive horizontal and vertical Lon-
    glines, creating robust on-chip bussing capability. The
    VersaBlock allows fast, local implementation of logic func-
    tions, effectively implementing user designs in a hierarchi-
    cal fashion. These resources also minimize local routing
    congestion and improve the efficiency of the general inter-
    connect, which is used for connecting larger groups of
    logic. It is this combination of both fine-grain and
    coarse-grain architecture attributes that maximize logic uti-
    lization in the XC5200 family. This symmetrical structure
    takes full advantage of the third metal layer, freeing the
    placement software to pack user logic optimally with mini-
    mal routing restrictions.
    VersaRing I/O Interface
    The interface between the IOBs and core logic has been
    redesigned in the XC5200 family. The IOBs are completely
    decoupled from the core logic. The XC5200 IOBs contain
    dedicated boundary-scan logic for added board-level test-
    ability, but do not include input or output registers. This
    approach allows a maximum number of IOBs to be placed
    around the device, improving the I/O-to-gate ratio and
    decreasing the cost per I/O. A “freeway” of interconnect
    cells surrounding the device forms the VersaRing, which
    provides connections from the IOBs to the internal logic.
    These incremental routing resources provide abundant
    connections from each IOB to the nearest VersaBlock, in
    addition to Longline connections surrounding the device.
    The VersaRing eliminates the historic trade-off between
    high logic utilization and pin placement flexibility. These
    incremental edge resources give users increased flexibility
    in preassigning (i.e., locking) I/O pins before completing
    their logic designs. This ability accelerates time-to-market,
    since PCBs and other system components can be manu-
    factured concurrent with the logic design.
    General Routing Matrix
    The GRM is functionally similar to the switch matrices
    found in other architectures, but it is novel in its tight cou-
    pling to the logic resources contained in the VersaBlocks.
    Advanced simulation tools were used during the develop-
    ment of the XC5200 architecture to determine the optimal
    level of routing resources required. The XC5200 family
    contains six levels of interconnect hierarchy — a series of
    Figure 4: Configurable Logic Block
    X4957
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    F3
    F
    FD
    LC3
    LC2
    LC1
    LC0
    F2
    F1
    D
    Q
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    CO
    F4
    F3
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    FD
    F2
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    F4
    F3
    F
    FD
    F2
    F1
    D
    Q
    X
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    DI
    F4
    F3
    F
    FD
    F2
    F1
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    Q
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    CI
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    CLR
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