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參數(shù)資料
| 型號(hào)： | XC4VSX25-12FFG668C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FPGA VIRTEX-4 SX 25K 668FCBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Virtex®-4 SX |
| LAB/CLB數(shù)： | 2560 |
| 邏輯元件/單元數(shù)： | 23040 |
| RAM 位總計(jì)： | 2359296 |
| 輸入/輸出數(shù)： | 320 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 668-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 668-FCBGA |
| 配用： | HW-AFX-FF668-400-ND - BOARD DEV VIRTEX 4 FF668 |
Virtex-4 Family Overview
DS112 (v3.1) August 30, 2010
Product Specification
5
R
range of signal delays. This is especially useful for synchro-
nizing signal edges in source synchronous interfaces.
General purpose I/O in select locations (four per bank) are
designed to be “regional clock capable” I/O by adding spe-
cial hardware connections for I/O in the same locality. These
regional clock inputs are distributed within a limited region
to minimize clock skew between IOBs. Regional I/O clock-
ing supplements the global clocking resources.
Data serializer/deserializer capability is added to every I/O
to support source synchronous interfaces. A serial-to-paral-
lel converter with associated clock divider is included in the
input path, and a parallel-to-serial converter in the output
path.
An in-depth guide to the Virtex-4 FPGA IOB is discussed in
Configurable Logic Blocks (CLBs)
A CLB resource is made up of four slices. Each slice is
equivalent and contains:
Two function generators (F & G)
Two storage elements
Arithmetic logic gates
Large multiplexers
Fast carry look-ahead chain
The function generators F & G are configurable as 4-input
look-up tables (LUTs). Two slices in a CLB can have their
LUTs configured as 16-bit shift registers, or as 16-bit distrib-
uted RAM. In addition, the two storage elements are either
edge-triggered D-type flip-flops or level sensitive latches.
Each CLB has internal fast interconnect and connects to a
switch matrix to access general routing resources.
The Virtex-4 FPGA CLBs are further discussed in the
Block RAM
The block RAM resources are 18 Kb true dual-port RAM
blocks, programmable from 16K x 1 to 512 x 36, in various
depth and width configurations. Each port is totally synchro-
nous and independent, offering three “read-during-write”
modes. Block RAM is cascadable to implement large
embedded storage blocks. Additionally, back-end pipeline
registers, clock control circuitry, built-in FIFO support, and
byte write enable are new features supported in the Virtex-4
FPGA.
The block RAM feature in Virtex-4 devices is further dis-
cussed in the Virtex-4 FPGA User Guide.
XtremeDSP Slices
The XtremeDSP slices contain a dedicated 18 x 18-bit 2’s
complement signed multiplier, adder logic, and a 48-bit
accumulator. Each multiplier or accumulator can be used
independently. These blocks are designed to implement
extremely efficient and high-speed DSP applications.
The block DSP feature in Virtex-4 devices are further dis-
cussed in XtremeDSP Design Considerations.
Global Clocking
The DCM and global-clock multiplexer buffers provide a
complete solution for designing high-speed clock networks.
Up to twenty DCM blocks are available. To generate
deskewed internal or external clocks, each DCM can be
used to eliminate clock distribution delay. The DCM also
provides 90°, 180°, and 270° phase-shifted versions of the
output clocks. Fine-grained phase shifting offers higher res-
olution phase adjustment with fraction of the clock period
increments. Flexible frequency synthesis provides a clock
output frequency equal to a fractional or integer multiple of
the input clock frequency.
Virtex-4 devices have 32 global-clock MUX buffers. The
clock tree is designed to be differential. Differential clocking
helps reduce jitter and duty cycle distortion.
Routing Resources
All components in Virtex-4 devices use the same intercon-
nect scheme and the same access to the global routing
matrix. Timing models are shared, greatly improving the
predictability of the performance for high-speed designs.
Boundary-Scan
Boundary-Scan instructions and associated data registers
support a standard methodology for accessing and config-
uring Virtex-4 devices, complying with IEEE standards
1149.1 and 1532.
Configuration
Virtex-4 devices are configured by loading the bitstream into
internal configuration memory using one of the following
modes:
Slave-serial mode
Master-serial mode
Slave SelectMAP mode
Master SelectMAP mode
Boundary-Scan mode (IEEE-1532)
Optional 256-bit AES decryption is supported on-chip (with
software bitstream encryption) providing Intellectual Prop-
erty security.
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| XC4VSX25-11FFG668I | IC FPGA VIRTEX-4 SX 25K 668FCBGA |
| XC4VLX40-11FFG668C | IC FPGA VIRTEX-4 LX 40K 668FCBGA |
| XC4VLX40-10FFG668I | IC FPGA VIRTEX-4 LX 40K 668FCBGA |
| XC5VLX50-1FF1153C | IC FPGA VIRTEX-5 50K 1153FBGA |
| XC2V2000-4BGG575C | IC FPGA VIRTEX-II 2M 575-MBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC4VSX35 | 制造商:XILINX 制造商全稱:XILINX 功能描述:DC and Switching Characteristics |
| XC4VSX35-10FF668C | 制造商:Xilinx 功能描述:FPGA VIRTEX-4 34560 CELLS 90NM 1.2V 668FCBGA - Trays |
| XC4VSX35-10FF668CES | 制造商:Xilinx 功能描述:FPGA, 3840 CLBS, 1028 MHZ, PBGA668 |
| XC4VSX3510FF668I | 制造商:XILINX 功能描述:New |
| XC4VSX35-10FF668I | 功能描述:IC FPGA VIRTEX-4SX 668FFBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex®-4 SX 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
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