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參數(shù)資料
| 型號(hào)： | XC4VLX80-11FFG1148I |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 8/9頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA VIRTEX-4 LX 80K 1148FBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Virtex®-4 LX |
| LAB/CLB數(shù)： | 8960 |
| 邏輯元件/單元數(shù)： | 80640 |
| RAM 位總計(jì)： | 3686400 |
| 輸入/輸出數(shù)： | 768 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 1148-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 1148-FCPBGA（35x35） |
Virtex-4 Family Overview
DS112 (v3.1) August 30, 2010
Product Specification
8
R
Virtex-4 Documentation
Complete and up-to-date documentation of the Virtex-4
family of FPGAs is available on the Xilinx web site. In addi-
tion to the most recent Virtex-4 Family Overview, the follow-
ing files are also available for download:
This data sheet contains the DC and Switching Characteris-
tic specifications for the Virtex-4 family.
This guide includes chapters on:
Clocking Resources
Digital Clock Manager (DCM)
Phase-Matched Clock Dividers (PMCD)
Block RAM and FIFO memory
Configurable Logic Blocks (CLBs)
SelectIO Resources
SelectIO Logic Resources
Advanced SelectIO Logic Resources
This guide describes the DSP48 slice and includes refer-
ence designs for using DSP48 math functions and various
FIR filters.
This all-encompassing configuration guide includes chap-
ters on configuration interfaces (serial and SelectMAP), bit-
stream encryption, Boundary-Scan and JTAG configuration,
and reconfiguration techniques.
This specification includes the tables for device/package
combinations and maximum I/Os, pin definitions, pinout
tables, pinout diagrams, mechanical drawings, and thermal
specifications.
This guide describes PCB guidelines for the Virtex-4 family.
It covers SelectIO signaling, RocketIO signaling, power dis-
tribution systems, PCB breakout, and parts placement.
This guide describes the RocketIO Multi-Gigabit Transceiv-
ers available in the Virtex-4 FX family.
This guide describes the Embedded Tri-Mode Ethernet
Media Access Controller available in the Virtex-4 FX family.
This guide is updated to include the PowerPC 405 proces-
sor block available in the Virtex-4 FX family.
Revision History
The following table shows the revision history for this document.
Date
Version
Revision
08/02/04
1.0
Initial Xilinx release. Printed Handbook version.
09/10/04
1.1
Typographical edits.
12/08/04
1.2
Removed System Monitor and ADC references.
Edited Ethernet MAC section.
03/26/05
1.3
Removed legacy CLB reference and typographical edits.
Edited serial transceiver sections.
In Table 2 added FFG Pb-Free packages.
06/17/05
1.4
Added note to Table 2 for SparseChevron pinouts.
02/10/06
1.5
Removed FCRAM-II support.
Added note 3 to Table 1.
Revised the CLB numbers for XC4VFX40 devices in Table 1.
Added stepping to order information example in Figure 1.
10/10/06
1.6
Changed maximum transceiver rate to 6.5 Gb/s.
Removed FF1760 package from Table 2.
01/23/07
2.0
Revision number jumped to 2.0 to correlate to data sheet (DS302) major revision.
Table 1: Corrected typo: XC4VFX40 number of slices = 18,624.
Table 2: Added column for FF676 package. Rewrote table footnotes.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC4VLX80-12FF1148C | 制造商:Xilinx 功能描述:FPGA VIRTEX-4 80640 CELLS 90NM 1.2V 1148FCBGA - Trays |
| XC4VLX80-12FFG1148C | 功能描述:IC FPGA VIRTEX-4 LX 80K 1148FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex®-4 LX 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XC4VSX25 | 制造商:XILINX 制造商全稱:XILINX 功能描述:DC and Switching Characteristics |
| XC4VSX25-10FF668C | 制造商:Xilinx 功能描述:FPGA VIRTEX-4 23040 CELLS 90NM 1.2V 668FCBGA - Trays |
| XC4VSX25-10FF668CES | 制造商:Xilinx 功能描述: |
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