參數(shù)資料
型號(hào)： XC4VLX160-10FFG1513C
廠(chǎng)商： Xilinx Inc
文件頁(yè)數(shù)： 2/9頁(yè)
文件大小： 0K
描述： IC FPGA VIRTEX-4LX 160K 1513FBGA
標(biāo)準(zhǔn)包裝： 1
系列： Virtex®-4 LX
LAB/CLB數(shù)： 16896
邏輯元件/單元數(shù)： 152064
RAM 位總計(jì)： 5308416
輸入/輸出數(shù)： 960
電源電壓： 1.14 V ~ 1.26 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 1513-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 1513-FCBGA（40x40）
Virtex-4 Family Overview
DS112 (v3.1) August 30, 2010
Product Specification
2
R
System Blocks Common to All Virtex-4 Families
Xesium Clock Technology
Up to twenty Digital Clock Manager (DCM) modules
-
Precision clock deskew and phase shift
-
Flexible frequency synthesis
-
Dual operating modes to ease performance trade-off
decisions
-
Improved maximum input/output frequency
-
Improved phase shifting resolution
-
Reduced output jitter
-
Low-power operation
-
Enhanced phase detectors
-
Wide phase shift range
Companion Phase-Matched Clock Divider (PMCD)
blocks
Differential clocking structure for optimized low-jitter
clocking and precise duty cycle
32 Global Clock networks
Regional I/O and Local clocks
Flexible Logic Resources
Up to 40% speed improvement over previous
generation devices
Up to 200,000 logic cells including:
-
Up to 178,176 internal registers with clock enable
(XC4VLX200)
-
Up to 178,176 look-up tables (LUTs)
-
Logic expanding multiplexers and I/O registers
Cascadable variable shift registers or distributed
memory capability
500 MHz XtremeDSP Slices
Dedicated 18-bit x 18-bit multiplier,
multiply-accumulator, or multiply-adder blocks
Optional pipeline stages for enhanced performance
Optional 48-bit accumulator for multiply accumulate
(MACC) operation
Integrated adder for complex-multiply or multiply-add
operation
Cascadeable Multiply or MACC
Up to 100% speed improvement over previous
generation devices.
500 MHz Integrated Block Memory
Up to 10 Mb of integrated block memory
Optional pipeline stages for higher performance
Multi-rate FIFO support logic
-
Full and Empty Flag support
-
Fully programmable AF and AE Flags
-
Synchronous/ Asynchronous Operation
Dual-port architecture
Independent read and write port width selection (RAM
only)
18 Kbit blocks (memory and parity/sideband memory
support)
Configurations from 16K x 1 to 512 x 36
(4K x 4 to 512 x 36 for FIFO operation)
Byte-write capability (connection to PPC405, etc.)
Dedicated cascade routing to form 32K x 1 memory
without using FPGA routing
Up to 100% speed improvement over previous
generation devices.
XC4VSX25
64 x 40
23,040
10,240
160
128
2,304
4
0
N/A
9
320
XC4VSX35
96 x 40
34,560
15,360
240
192
3,456
8
4
N/A
11
448
XC4VSX55
128 x 48
55,296
24,576
384
512
320
5,760
8
4
N/A
13
640
XC4VFX12
64 x 24
12,312
5,472
86
32
36
648
4
0
1
2
N/A
9
320
XC4VFX20
64 x 36
19,224
8,544
134
32
68
1,224
4
0
1
2
8
9
320
XC4VFX40
96 x 52
41,904
18,624
291
48
144
2,592
8
4
2
4
12
11
448
XC4VFX60
128 x 52
56,880
25,280
395
128
232
4,176
12
8
2
4
16
13
576
XC4VFX100
160 x 68
94,896
42,176
659
160
376
6,768
12
8
2
4
20
15
768
XC4VFX140
192 x 84
142,128
63,168
987
192
552
9,936
20
8
2
4
24
17
896
Notes:
1.
One CLB = Four Slices = Maximum of 64 bits.
2.
Each XtremeDSP slice contains one 18 x 18 multiplier, an adder, and an accumulator
3.
Some of the row/column array is used by the processors in the FX devices.
Table 1: Virtex-4 FPGA Family Members (Continued)
Device
Configurable Logic Blocks (CLBs)(1)
XtremeDSP
Slices(2)
Block RAM
DCMs PMCDs
PowerPC
Processor
Blocks
Ethernet
MACs
RocketIO
Transceiver
Blocks
Total
I/O
Banks
Max
User
I/O
Array(3)
Row x Col
Logic
Cells
Slices
Max
Distributed
RAM (Kb)
18 Kb
Blocks
Max
Block
RAM (Kb)
相關(guān)PDF資料
PDF描述
ASC50DRYI CONN EDGECARD 100PS .100 DIP SLD
ACB100DHRR CONN CARD EXTEND 200POS .050"
ABB100DHRR CONN CARD EXTEND 200POS .050"
ACC60DRXS-S734 CONN EDGECARD 120PS DIP .100 SLD
HMC15DTEN CONN EDGECARD 30POS .100 EYELET
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC4VLX160-10FFG1513I 功能描述:IC FPGA VIRTEX-4LX 160K 1513FBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex®-4 LX 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
XC4VLX160-11FF1148I 功能描述:IC FPGA VIRTEX-4LX 1148FFBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex®-4 LX 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
XC4VLX160-11FF1513C 制造商:Xilinx 功能描述:FPGA VIRTEX-4 152064 CELLS 90NM 1.2V 1513FCBGA - Trays
XC4VLX160-11FF1513I 功能描述:IC FPGA VIRTEX-4LX 1513FFBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex®-4 LX 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
XC4VLX160-11FFG1148C 功能描述:IC FPGA VIRTEX-4LX 160K 1148FBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex®-4 LX 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*