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參數(shù)資料
| 型號： | XC4VLX100-10FFG1148I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 6/9頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA VIRTEX-4LX 100K 1148FBGA |
| 標準包裝： | 1 |
| 系列： | Virtex®-4 LX |
| LAB/CLB數(shù)： | 12288 |
| 邏輯元件/單元數(shù)： | 110592 |
| RAM 位總計： | 4423680 |
| 輸入/輸出數(shù)： | 768 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 1148-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 1148-FCPBGA（35x35） |
Virtex-4 Family Overview
DS112 (v3.1) August 30, 2010
Product Specification
6
R
Virtex-4 FX Family
This section briefly describes blocks available only in FX devices.
RocketIO Multi-Gigabit Transceiver
8 – 24 Channels RocketIO Multi-Gigabit Serial Transceivers
(MGTs) capable of running 622 Mb/s – 6.5 Gb/s
Full Clock and Data Recovery
32-bit or 40-bit datapath support
Optional 8B/10B, 64B/66B, or FPGA-based
encode/decode
Integrated FIFO/Elastic Buffer
Support for Channel Bonding
Embedded 32-bit CRC generation/checking
Integrated Comma-detect or programmable A1/A2,
A1A1/A2A2 detection
Programmable pre-emphasis (AKA transmitter
equalization)
Programmable receiver equalization
Embedded support for:
-
Out of Band (OOB) Signalling: Serial ATA
-
Beaconing and Electrical Idle: PCI-Express
On-chip bypassable AC coupling for receiver
One or Two PowerPC 405 Processor Cores
32-bit Harvard Architecture
5-Stage Execution Pipeline
Integrated 16KB Level 1 Instruction Cache and 16KB
Level 1 Data Cache
Integrated Level 1 Cache Parity Generation and
Checking
CoreConnect Bus Architecture
Efficient, high-performance on-chip memory (OCM)
interface to block RAM
PLB Synchronization Logic (Enables Non-Integer
CPU-to-PLB Clock Ratios)
Auxiliary Processor Unit (APU) Interface and Integrated
APU Controller
-
Optimized FPGA-based Coprocessor connection
-
Automatic decode of PowerPC floating-point instructions
— allows custom instructions (decode for up to eight
instructions)
-
Extremely efficient microcontroller-style interfacing
Two or Four Tri-Mode (10/100/1000 Mb/s) Ethernet Media Access Control (MAC) Cores
IEEE 802.3-2000 Compliant
MII/GMII Interface or SGMII (when used with RocketIO
Transceivers)
Can Operate Independent of PowerPC processor
Half- or Full-Duplex
Supports Jumbo Frames
1000Base-X PCS/PMA: When used with RocketIO
MGT can provide complete 1000Base-X
implementation on-chip
Intellectual Property Cores
Xilinx offers IP cores for commonly used complex functions
including DSP, bus interfaces, processors, and processor
peripherals. Using Xilinx LogiCORE products and cores
from third party AllianceCORE participants, customers can
shorten development time, reduce design risk, and obtain
superior performance for their designs. Additionally, our
CORE Generator system allows customers to implement
IP cores into Virtex-4 FPGAs with predictable and repeat-
able performance. It offers a simple user interface to gener-
ate parameter-based cores optimized for our FPGAs.
The System Generator for DSP tool allows system archi-
tects to quickly model and implement DSP functions using
handcrafted IP, and features an interface to third-party sys-
tem level DSP design tools. System Generator for DSP
implements many of the high-performance DSP cores sup-
porting Virtex-4 FPGAs including the Xilinx Forward Error
Correction
Solution
with
Interleaver/De-interleaver,
Reed-Solomon encoder/decoders, and Viterbi decoders.
These are ideal for creating highly-flexible, concatenated
codecs to support the communications market.
Industry leading connectivity and networking IP cores
include the electronics industry's first Advanced Switching
product, leading-edge PCI Express, Serial RapidIO, Fibre
Channel, and 10Gb Ethernet cores that include Virtex-4
FPGA RocketIO multi-gigabit serial interfaces. The Xilinx
SPI-4.2 IP core utilizes the Virtex-4 FPGA embedded
ChipSync technology to implement dynamic phase align-
ment for high-performance source-synchronous operation.
MicroBlaze processor 32-bit core provides the industry's
fastest soft processing solution for building complex sys-
tems for the networking, telecommunication, data communi-
cation, embedded and consumer markets. The MicroBlaze
processor features a RISC architecture with Harvard-style
separate 32-bit instruction and data busses running at full
speed to execute programs and access data from both
on-chip and external memory. A standard set of peripherals
are also CoreConnect enabled to offer MicroBlaze pro-
cessor designers compatibility and reuse.
All IP cores for Virtex-4 FPGAs are found on the Xilinx IP
Center Internet portal presenting the latest intellectual prop-
erty cores and reference designs via Smart Search for
faster access.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC4VLX100-10FFG1513C | 功能描述:IC FPGA VIRTEX-4 100K 1513-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-4 LX 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XC4VLX100-10FFG1513I | 功能描述:IC FPGA VIRTEX-4LX 100K 1513FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-4 LX 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XC4VLX100-11FF1148C | 制造商:Xilinx 功能描述:FPGA VIRTEX-4 110592 CELLS 90NM 1.2V 1148FCBGA - Trays |
| XC4VLX100-11FF1148I | 功能描述:IC FPGA VIRTEX-4LX 1148FFBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-4 LX 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XC4VLX100-11FF1513C | 制造商:Xilinx 功能描述:FPGA VIRTEX-4 110592 CELLS 90NM 1.2V 1513FCBGA - Trays |
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