參數(shù)資料
型號: XC4VFX12-11FF668I
廠商: Xilinx Inc
文件頁數(shù): 22/58頁
文件大?。?/td> 0K
描述: IC FPGA VIRTEX-4FX 668FFBGA
標準包裝: 40
系列: Virtex®-4 FX
LAB/CLB數(shù): 1368
邏輯元件/單元數(shù): 12312
RAM 位總計: 663552
輸入/輸出數(shù): 320
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 668-BBGA,F(xiàn)CBGA
供應商設備封裝: 668-FCBGA
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
29
Input Delay Switching Characteristics
Table 35: Input Delay Switching Characteristics
Symbol
Description
Speed Grade
Units
-12
-11
-10
IDELAYCTRL
TIDELAYCTRLCO_RDY
Reset to Ready for IDELAYCTRL
(Maximum)
3.00
s
FIDELAYCTRL_REF
REFCLK frequency
200
MHz
IDELAYCTRL_REF_PRECISION(2)
REFCLK precision
±10
MHz
TIDELAYCTRL_RPW
Minimum Reset pulse width
50.0
ns
IDELAY
TIDELAYRESOLUTION
IDELAY Chain Delay Resolution
75
ps
TIDELAYTOTAL_ERR
Cumulative delay at a given tap(3)
[(tap
1) x 75 +34]
± 0.07[(tap 1) x 75 +34]
ps
TIDELAYPAT_JIT
Pattern dependent period jitter in delay
chain for clock pattern
00
0
Note (4)
Pattern dependent period jitter in delay
chain for random data pattern (PRBS 23)
10 ± 2
Note (4)
FMAX
C clock maximum frequency
300
250
MHz
Notes:
1.
Refer to Xilinx Application Note XAPP707 for details on IDELAY timing characteristics.
2.
See the “REFCLK - Reference Clock” section (specific to IDELAYCTRL) in the Virtex-4 FPGA User Guide: Chapter 7, SelectIO Logic Resources.
3.
This value accounts for tap 0, an anomaly in the tap chain with an average value of 34 ps.
4.
Units in ps peak-to-peak per tap.
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