參數(shù)資料
型號(hào)： XC4VFX12-10SFG363I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 47/58頁(yè)
文件大小： 0K
描述： IC FPGA VIRTEX-4 FX 12K 363FCBGA
標(biāo)準(zhǔn)包裝： 90
系列： Virtex®-4 FX
LAB/CLB數(shù)： 1368
邏輯元件/單元數(shù)： 12312
RAM 位總計(jì)： 663552
輸入/輸出數(shù)： 240
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 363-FBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 363-FCBGA（17x17）
配用： HW-V4-ML403-UNI-G-ND - EVALUATION PLATFORM VIRTEX-4
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
51
Production Stepping
The Virtex-4 FPGA stepping identification system denotes
the capability improvement of production released devices.
By definition, devices from one stepping are functional
supersets of previous devices. Bitstreams compiled for a
device with an earlier stepping are guaranteed to operate
correctly in subsequent device steppings.
New device steppings can be shipped in place of earlier
device steppings. Existing production designs are guaran-
teed on new device steppings. To take advantage of the
capabilities of a newer device stepping, customers are able
to order a new stepping version and compile a new bit-
stream.
Production devices are marked with a stepping version, with
the exception of some step 1 devices. Designs should be
compiled with a CONFIG STEPPING parameter set to a
specific stepping version. This parameter is set in the UCF
file:
CONFIG STEPPING = “#”; (where # is the stepping
version)
The default stepping level used by the ISE software is
reported in the PAR report.
Table 63 shows the JTAG ID code by step.
Table 61: Sample Window
Symbol
Description
Device
Speed Grade
Units
-12
-11
-10
TSAMP
Sampling Error at Receiver Pins(1)
All
450
500
550
ps
TSAMP_BUFIO
Sampling Error at Receiver Pins using BUFIO(2)
All
350
400
450
ps
Notes:
1.
This parameter indicates the total sampling error of Virtex-4 FPGA DDR input registers across voltage, temperature, and process. The
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include:
- CLK0 DCM jitter
- DCM accuracy (phase offset)
- DCM phase shift resolution
These measurements do not include package or clock tree skew.
2.
This parameter indicates the total sampling error of Virtex-4 FPGA DDR input registers across voltage, temperature, and process. The
characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of operation. These
measurements do not include package or clock tree skew.
Table 62: ChipSync Pin-to-Pin Setup/Hold and Clock-to-Out
Symbol
Description
Speed Grade
Units
-12
-11
-10
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
TPSCS /TPHCS
Setup/Hold of I/O clock across multiple clock regions
–0.45
0.97
–0.45
1.08
–0.44
1.17
ns
Pin-to-Pin Clock-to-Out Using BUFIO
TICKOFCS
Clock-to-Out of I/O clock across multiple clock regions
4.10
4.54
5.02
ns
Table 63: JTAG ID Code by Step
Device
Step 0
Step 1
Step 2
XC4VLX15
35
XC4VLX25
9A
XC4VLX40
35
XC4VLX60
2 or 3
4 or 5
XC4VLX80
35
XC4VLX100
2 or 3
4 or 5
XC4VLX160
0 or 3
4 or 5
XC4VLX200
0 or 3
2 or 5
XC4VSX25
24
XC4VSX35
24
XC4VSX55
24
XC4VFX12
0 or 2
XC4VFX20
26
XC4VFX40
0
XC4VFX60
28
XC4VFX100
06
XC4VFX140
04
Notes:
1.
Shaded cells represent devices not produced at that stepping.
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