參數(shù)資料
型號: XC4VFX12-10FFG668C
廠商: Xilinx Inc
文件頁數(shù): 42/58頁
文件大小: 0K
描述: IC FPGA VIRTEX-4 FX 12K 668FCBGA
標(biāo)準(zhǔn)包裝: 40
系列: Virtex®-4 FX
LAB/CLB數(shù): 1368
邏輯元件/單元數(shù): 12312
RAM 位總計: 663552
輸入/輸出數(shù): 320
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 668-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 668-FCBGA
配用: HW-V4-ML403-UNI-G-ND - EVALUATION PLATFORM VIRTEX-4
HW-AFX-FF668-400-ND - BOARD DEV VIRTEX 4 FF668
其它名稱: 122-1591
XC4VFX12-10FFG668C-ND
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
47
Table 57: Global Clock Setup and Hold for LVCMOS25 Standard, with DCM in Source-Synchronous Mode
Symbol
Description
Device
Speed Grade
Units
12
11
10
Example Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin,(1) Using DCM and Global Clock Buffer. For
situations where clock and data inputs conform to different standards, adjust the setup and hold values accordingly using the values
TPSDCM_0 /
TPHDCM_0
No Delay Global Clock and IFF(2) with DCM in
Source-Synchronous Mode
XC4VLX15
–0.33
0.73
–0.33
0.88
–0.33
1.03
ns
XC4VLX25
–0.29
0.86
–0.29
0.97
–0.29
1.09
ns
XC4VLX40
–0.37
0.90
–0.37
1.04
–0.37
1.19
ns
XC4VLX60
–0.32
1.02
–0.32
1.15
–0.32
1.29
ns
XC4VLX80
–0.38
1.18
–0.38
1.34
–0.38
1.50
ns
XC4VLX100
–0.31
1.24
–0.31
1.41
–0.31
1.57
ns
XC4VLX160
–0.31
1.50
–0.31
1.69
–0.31
1.89
ns
XC4VLX200
N/A
–0.31
1.97
–0.31
2.19
ns
XC4VSX25
–0.32
0.95
–0.32
1.07
–0.32
1.17
ns
XC4VSX35
–0.37
1.04
–0.37
1.17
–0.37
1.31
ns
XC4VSX55
–0.32
1.22
–0.32
1.36
–0.32
1.52
ns
XC4VFX12
–0.26
0.73
–0.26
0.86
–0.26
0.96
ns
XC4VFX20
–0.31
0.92
–0.31
1.03
–0.31
1.14
ns
XC4VFX40
–0.35
1.26
–0.35
1.41
–0.35
156
ns
XC4VFX60
–0.43
1.39
–0.43
1.56
–0.43
1.74
ns
XC4VFX100
–0.38
1.55
–0.38
1.75
–0.38
1.96
ns
XC4VFX140
N/A
–0.44
2.03
–0.44
2.25
ns
Notes:
1.
The timing values were measured using the fine-phase adjustment feature of the DCM. These measurements include CLK0 DCM jitter. Package
skew is not included in these measurements.
2.
IFF = Input Flip-Flop
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