參數(shù)資料
型號: XC4028EX-3HQ208C
廠商: Xilinx Inc
文件頁數(shù): 58/68頁
文件大?。?/td> 0K
描述: IC FPGA 1024 CLB'S 208-HQFP
標(biāo)準(zhǔn)包裝: 24
系列: XC4000E/X
LAB/CLB數(shù): 1024
邏輯元件/單元數(shù): 2432
RAM 位總計: 32768
輸入/輸出數(shù): 160
門數(shù): 28000
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 208-BFQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
其它名稱: 122-1127
R
May 14, 1999 (Version 1.6)
6-65
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Figure 57: Synchronous Peripheral Mode Programming Switching Characteristics
0
DOUT
CCLK
1
2
345
6
7
BYTE
0
BYTE
1
BYTE 0 OUT
BYTE 1 OUT
RDY/BUSY
INIT
1
0
X6096
Description
Symbol
Min
Max
Units
CCLK
INIT (High) setup time
TIC
5
s
D0 - D7 setup time
TDC
60
ns
D0 - D7 hold time
TCD
0ns
CCLK High time
TCCH
50
ns
CCLK Low time
TCCL
60
ns
CCLK Frequency
FCC
8
MHz
Notes:
1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the
rst data byte on the second rising edge of CCLK after INIT goes High. Subsequent data bytes are clocked in on every
eighth consecutive rising edge of CCLK.
2. The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation does
not require such a response.
3. The pin name RDY/BUSY is a misnomer. In Synchronous Peripheral mode this is really an ACKNOWLEDGE signal.
4. Note that data starts to shift out serially on the DOUT pin 0.5 CCLK periods after it was loaded in parallel. Therefore,
additional CCLK pulses are clearly required after the last byte has been loaded.
Product Obsolete or Under Obsolescence
相關(guān)PDF資料
PDF描述
XC4028EX-2HQ208C IC FPGA 1024 CLB'S 208-HQFP
IDT71V424L15PHGI8 IC SRAM 4MBIT 15NS 44TSOP
IDT7164S25YGI IC SRAM 64KBIT 25NS 28SOJ
XC4025E-3HQ240C IC FPGA 1024 CLB'S 240-HQFP
XC4013E-3PQ160C IC FPGA 576 CLB'S 160-PQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC4028EX-3HQ208I 制造商:Xilinx 功能描述:
XC4028EX-3HQ240C 制造商:Xilinx 功能描述:
XC4028EX-3HQ240I 制造商:Xilinx 功能描述:
XC4028EX-3HQ304C 制造商:Xilinx 功能描述:
XC4028EX-4BG352I 制造商:Xilinx 功能描述: 制造商:Xilinx 功能描述:FPGA, 1024 CLBS, 18000 GATES, 143 MHz, PBGA352