參數(shù)資料
型號(hào): XC4025E-4CBG228M
廠商: XILINX INC
元件分類: FPGA
英文描述: FPGA, 1024 CLBS, 15000 GATES, 111 MHz, CQFP228
封裝: CERAMIC, QFP-228
文件頁數(shù): 1/23頁
文件大?。?/td> 138K
代理商: XC4025E-4CBG228M
November 21, 1997 (Version 1.3)
8-11
XC4000E High-Reliability Features
System featured Field-Programmable Gate Arrays
-
Select-RAMTM memory: on-chip ultra-fast RAM with
-
synchronous write option
-
dual-port RAM option
-
Abundant ip-ops
-
Flexible function generators
-
Dedicated high-speed carry logic
-
Wide edge decoders on each edge
-
Hierarchy of interconnect lines
-
Internal 3-state bus capability
-
8 global low-skew clock or signal distribution
networks
System Performance beyond 60 MHz
Flexible Array Architecture
Low Power Segmented Routing Architecture
Systems-Oriented Features
-
IEEE 1149.1-compatible boundary scan logic
support
-
Individually programmable output slew rate
-
Programmable input pull-up or pull-down resistors
-
12-mA sink current per XC4000E output
Congured by Loading Binary File
-
Unlimited reprogrammability
Readback Capability
-
Program verication
-
Internal node observability
Backward Compatible with XC4000 Devices
Development System runs on most common computer
platforms
-
Interfaces to popular design environments
-
Fully automatic mapping, placement and routing
-
Interactive design editor for design optimization
Available in class Q fully compliant QML and Military
temperature range only
-
Certied to MIL-PRF-38535, appendix A QML
(Qualied Manufacturers Listing)
Xilinx High-Reliability
XC4000E family is supplied under the following standard
microcircuit drawings (SMDs):
XC4005E 5962-97522
XC4010E 5962-97523
XC4013E 5962-97524
XC4025E 5962-97525
For more information contact DSCC (Defense Supply Cen-
ter Columbus) Columbus, Ohio.
* Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
0
XC4000E High-Reliability
Field Programmable Gate Arrays
November 21, 1997 (Version 1.3)
08*
Product Specification
Table 1: XC4000E Field Programmable Gate Arrays
Device
Max.
Logic
Gates
(No RAM)
Max. RAM
Bits
(No Logic)
Typical
Gate Range
(Logic and
RAM)*
CLB
Matrix
Total
CLBs
Number
of
Flip-Flops
Max.
Decode
Inputs
per side
Max.
User I/O
Packages
XC4005E
5,000
6,272
3,000 - 9,000
14 x 14
196
616
42
112
PG156,
CB164
XC4010E
10,000
12,800
7,000 - 20,000 20 x 20
400
1,120
60
160
PG191,
CB196
XC4013E
13,000
18,432
10,000 -
30,000
24 x 24
576
1,536
72
192
PG223,
CB228
XC4025E
25,000
32,768
15,000 -
45,000
32 x 32
1,024
2,560
96
256
PG299,
CB228
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