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| 型號： | XC4025E-2HQ240C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 27/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1024 CLB'S 240-HQFP |
| 產(chǎn)品變化通告： | XC4000(XL,XLA,E) Discontinuation 15/Nov/2004 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | XC4000E/X |
| LAB/CLB數(shù)： | 1024 |
| 邏輯元件/單元數(shù)： | 2432 |
| RAM 位總計(jì)： | 32768 |
| 輸入/輸出數(shù)： | 193 |
| 門數(shù)： | 25000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 240-BFQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 240-PQFP（32x32） |
| 其它名稱： | 122-1118 |
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R
May 14, 1999 (Version 1.6)
6-37
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Global Nets and Buffers (XC4000X only)
Eight vertical longlines in each CLB column are driven by
special global buffers. These longlines are in addition to the
vertical longlines used for standard interconnect. The glo-
bal lines are broken in the center of the array, to allow faster
distribution and to minimize skew across the whole array.
Each half-column global line has its own buffered multi-
plexer, as shown in Figure 35. The top and bottom global
lines cannot be connected across the center of the device,
as this connection might introduce unacceptable skew. The
top and bottom halves of the global lines must be sepa-
rately driven — although they can be driven by the same
global buffer.
The eight global lines in each CLB column can be driven by
either of two types of global buffers. They can also be
driven by internal logic, because they can be accessed by
single, double, and quad lines at the top, bottom, half, and
quarter points. Consequently, the number of different
clocks that can be used simultaneously in an XC4000X
device is very large.
There are four global lines feeding the IOBs at the left edge
of the device. IOBs along the right edge have eight global
lines. There is a single global line along the top and bottom
edges with access to the IOBs. All IOB global lines are bro-
ken at the center. They cannot be connected across the
center of the device, as this connection might introduce
unacceptable skew.
IOB global lines can be driven from two types of global buff-
ers, or from local interconnect. Alternatively, top and bottom
IOBs can be clocked from the global lines in the adjacent
CLB column.
Two different types of clock buffers are available in the
XC4000X:
Global Low-Skew Buffers (BUFGLS)
Global Early Buffers (BUFGE)
Global Low-Skew Buffers are the standard clock buffers.
They should be used for most internal clocking, whenever a
large portion of the device must be driven.
Global Early Buffers are designed to provide a faster clock
access, but CLB access is limited to one-fourth of the
device. They also facilitate a faster I/O interface.
Figure 35 is a conceptual diagram of the global net struc-
ture in the XC4000X.
Global Early buffers and Global Low-Skew buffers share a
single pad. Therefore, the same IPAD symbol can drive one
buffer of each type, in parallel. This conguration is particu-
larly useful when using the Fast Capture latches, as
described in “IOB Input Signals” on page 20. Paired Global
Early and Global Low-Skew buffers share a common input;
they cannot be driven by two different signals.
Choosing an XC4000X Clock Buffer
The clocking structure of the XC4000X provides a large
variety of features. However, it can be simple to use, with-
out understanding all the details. The software automati-
cally handles clocks, along with all other routing, when the
appropriate clock buffer is placed in the design. In fact, if a
buffer symbol called BUFG is placed, rather than a specic
type of buffer, the software even chooses the buffer most
appropriate for the design. The detailed information in this
section is provided for those users who want a ner level of
control over their designs.
If ne control is desired, use the following summary and
Table 15 on page 35 to choose an appropriate clock buffer.
The simplest thing to do is to use a Global Low-Skew
buffer.
If a faster clock path is needed, try a BUFG. The
software will rst try to use a Global Low-Skew Buffer. If
timing requirements are not met, a faster buffer will
automatically be used.
If a single quadrant of the chip is sufcient for the
clocked logic, and the timing requires a faster clock than
the Global Low-Skew buffer, use a Global Early buffer.
Global Low-Skew Buffers
Each corner of the XC4000X device has two Global
Low-Skew buffers. Any of the eight Global Low-Skew buff-
ers can drive any of the eight vertical Global lines in a col-
umn of CLBs. In addition, any of the buffers can drive any of
the four vertical lines accessing the IOBs on the left edge of
the device, and any of the eight vertical lines accessing the
IOBs on the right edge of the device. (See Figure 36 on
IOBs at the top and bottom edges of the device are
accessed through the vertical Global lines in the CLB array,
as in the XC4000E. Any Global Low-Skew buffer can,
therefore, access every IOB and CLB in the device.
The Global Low-Skew buffers can be driven by either
semi-dedicated pads or internal logic.
To use a Global Low-Skew buffer, instantiate a BUFGLS
element in a schematic or in HDL code. If desired, attach a
LOC attribute or property to direct placement to the desig-
nated location. For example, attach a LOC=T attribute or
property to direct that a BUFGLS be placed in one of the
two Global Low-Skew buffers on the top edge of the device,
or a LOC=TR to indicate the Global Low-Skew buffer on the
top edge of the device, on the right.
Product Obsolete or Under Obsolescence
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