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參數(shù)資料
| 型號： | XC4020E-3HQ240C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 10/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 784 CLB'S 240-HQFP |
| 產(chǎn)品變化通告： | XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | XC4000E/X |
| LAB/CLB數(shù)： | 784 |
| 邏輯元件/單元數(shù)： | 1862 |
| RAM 位總計： | 25088 |
| 輸入/輸出數(shù)： | 193 |
| 門數(shù)： | 20000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 240-BFQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 240-PQFP（32x32） |
| 其它名稱： | 122-1117 |
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R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-22
May 14, 1999 (Version 1.6)
XC4000XL 5-Volt Tolerant I/Os
The I/Os on the XC4000XL are fully 5-volt tolerant even
though the VCC is 3.3 volts. This allows 5 V signals to
directly connect to the XC4000XL inputs without damage,
applied before or after 5 volt signals are applied to the I/Os.
This makes the XC4000XL immune to power supply
sequencing problems.
Registered Inputs
The I1 and I2 signals that exit the block can each carry
either the direct or registered input signal.
The input and output storage elements in each IOB have a
common clock enable input, which, through conguration,
can be activated individually for the input or output ip-op,
or both. This clock enable operates exactly like the EC pin
on the XC4000 Series CLB. It cannot be inverted within the
IOB.
The storage element behavior is shown in Table 9.
Table 9: Input Register Functionality
(active rising edge is shown)
Optional Delay Guarantees Zero Hold Time
The data input to the register can optionally be delayed by
several nanoseconds. With the delay enabled, the setup
time of the input ip-op is increased so that normal clock
routing does not result in a positive hold-time requirement.
A positive hold time requirement can lead to unreliable,
temperature- or processing-dependent operation.
The input ip-op setup time is dened between the data
measured at the device I/O pin and the clock input at the
IOB (not at the clock pin). Any routing delay from the device
clock pin to the clock input of the IOB must, therefore, be
subtracted from this setup time to arrive at the real setup
time requirement relative to the device pins. A short speci-
ed setup time might, therefore, result in a negative setup
time at the device pins, i.e., a positive hold-time require-
ment.
When a delay is inserted on the data line, more clock delay
can be tolerated without causing a positive hold-time
requirement. Sufcient delay eliminates the possibility of a
data hold-time requirement at the external pin. The maxi-
mum delay is therefore inserted as the default.
The XC4000E IOB has a one-tap delay element: either the
delay is inserted (default), or it is not. The delay guarantees
a zero hold time with respect to clocks routed through any
of the XC4000E global clock buffers. (See “Global Nets and
Buffers (XC4000E only)” on page 35 for a description of the
global clock buffers in the XC4000E.) For a shorter input
register setup time, with non-zero hold, attach a NODELAY
attribute or property to the ip-op.
The XC4000X IOB has a two-tap delay element, with
choices of a full delay, a partial delay, or no delay. The
attributes or properties used to select the desired delay are
shown in Table 10. The choices are no added attribute,
MEDDELAY, and NODELAY. The default setting, with no
added attribute, ensures no hold time with respect to any of
the XC4000X clock buffers, including the Global Low-Skew
buffers. MEDDELAY ensures no hold time with respect to
the Global Early buffers. Inputs with NODELAY may have a
positive hold time with respect to all clock buffers. For a
description of each of these buffers, see “Global Nets and
Table 10: XC4000X IOB Input Delay Element
Table 8: Supported Sources for XC4000 Series Device
Inputs
Source
XC4000E/EX
Series Inputs
XC4000XL
Series Inputs
5 V,
TTL
5 V,
CMOS
3.3 V
CMOS
Any device, Vcc = 3.3 V,
CMOS outputs
√
Unreli
-able
Data
√
XC4000 Series, Vcc = 5 V,
TTL outputs
√√
Any device, Vcc = 5 V,
TTL outputs (Voh
≤ 3.7 V)
√√
Any device, Vcc = 5 V,
CMOS outputs
√√
√
Mode
Clock
Enable
DQ
Power-Up or
GSR
XX
X
SR
Flip-Flop
__/
1*
D
0X
X
Q
Latch
1
1*
X
Q
01*
D
Both
X
0
X
Q
Legend:
X
__/
SR
0*
1*
Don’t care
Rising edge
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
Value
When to Use
full delay
(default, no
attribute added)
Zero Hold with respect to Global
Low-Skew Buffer, Global Early Buffer
MEDDELAY
Zero Hold with respect to Global Early
Buffer
NODELAY
Short Setup, positive Hold time
Product Obsolete or Under Obsolescence
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