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參數(shù)資料
| 型號(hào)： | XC4020E-2HQ240C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 39/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 784 CLB'S 240-HQFP |
| 產(chǎn)品變化通告： | XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | XC4000E/X |
| LAB/CLB數(shù)： | 784 |
| 邏輯元件/單元數(shù)： | 1862 |
| RAM 位總計(jì)： | 25088 |
| 輸入/輸出數(shù)： | 193 |
| 門數(shù)： | 20000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 240-BFQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 240-PQFP（32x32） |
| 其它名稱： | 122-1116 |
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R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-48
May 14, 1999 (Version 1.6)
Setting CCLK Frequency
For Master modes, CCLK can be generated in either of two
frequencies. In the default slow mode, the frequency
ranges from 0.5 MHz to 1.25 MHz for XC4000E and
XC4000EX devices and from 0.6 MHz to 1.8 MHz for
XC4000XL devices. In fast CCLK mode, the frequency
ranges from 4 MHz to 10 MHz for XC4000E/EX devices and
from 5 MHz to 15 MHz for XC4000XL devices. The fre-
quency is selected by an option when running the bitstream
generation software. If an XC4000 Series Master is driving
an XC3000- or XC2000-family slave, slow CCLK mode
must be used. In addition, an XC4000XL device driving a
XC4000E or XC4000EX should use slow mode. Slow mode
is the default.
Table 19: XC4000 Series Data Stream Formats
Data Stream Format
The data stream (“bitstream”) format is identical for all con-
guration modes.
The data stream formats are shown in Table 19. Bit-serial
data is read from left to right, and byte-parallel data is effec-
tively assembled from this serial bitstream, with the rst bit
in each byte assigned to D0.
The conguration data stream begins with a string of eight
ones, a preamble code, followed by a 24-bit length count
and a separator eld of ones. This header is followed by the
actual conguration data in frames. The length and number
of frames depends on the device type (see Table 20 and
Table 21). Each frame begins with a start eld and ends
with an error check. A postamble code is required to signal
the end of data for a single device. In all cases, additional
start-up bytes of data are required to provide four clocks for
the startup sequence at the end of conguration. Long
daisy chains require additional startup bytes to shift the last
data through the chain. All startup bytes are don’t-cares;
these bytes are not included in bitstreams created by the
Xilinx software.
A selection of CRC or non-CRC error checking is allowed
by the bitstream generation software. The non-CRC error
checking tests for a designated end-of-frame eld for each
frame. For CRC error checking, the software calculates a
running CRC and inserts a unique four-bit partial check at
the end of each frame. The 11-bit CRC check of the last
frame of an FPGA includes the last seven data bits.
Detection of an error results in the suspension of data load-
ing and the pulling down of the INIT pin. In Master modes,
CCLK and address signals continue to operate externally.
The user must detect INIT and initialize a new conguration
by pulsing the PROGRAM pin Low or cycling Vcc.
Data Type
All Other
Modes (D0...)
Fill Byte
11111111b
Preamble Code
0010b
Length Count
COUNT(23:0)
Fill Bits
1111b
Start Field
0b
Data Frame
DATA(n-1:0)
CRC or Constant
Field Check
xxxx (CRC)
or 0110b
Extend Write Cycle
—
Postamble
01111111b
Start-Up Bytes
xxh
Legend:
Not shaded
Once per bitstream
Light
Once per data frame
Dark
Once per device
Product Obsolete or Under Obsolescence
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