參數資料
型號: XC4013XL-2BG256I
廠商: Xilinx Inc
文件頁數: 16/16頁
文件大小: 0K
描述: IC FPGA I-TEMP 3.3V 2SPD 256PBGA
產品變化通告: Product Discontinuation 27/Apr/2010
標準包裝: 1
系列: XC4000E/X
LAB/CLB數: 576
邏輯元件/單元數: 1368
RAM 位總計: 18432
輸入/輸出數: 192
門數: 13000
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 256-BBGA
供應商設備封裝: 256-PBGA
R
DS005 (v2.0) March 1, 2013 - Product Specification
6-81
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Product Obsolete/Under Obsolescence
Output Flip-Flop, Clock to Out, BUFGE #s 1, 2, 5, and 6
Output Flip-Flop, Clock to Out, BUFGE #s 3, 4, 7, and 8
Speed Grade
All
-3
-2
-1
-09
-08
Units
Description
Symbol
Device
Min
Max
Global Early Clock to Output using
Output Flip Flop. Values are for
BUFGE #s 1, 2, 5, and 6.
TICKEOF
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
1.0
1.2
1.3
1.2
1.1
1.2
1.3
6.6
6.9
7.2
7.4
7.6
7.8
8.1
8.5
9.0
9.9
10.8
5.7
6.1
6.2
6.4
6.5
6.7
7.0
7.3
7.8
8.6
9.4
5.1
5.5
5.6
5.9
6.1
6.4
6.8
7.5
8.5
4.8
5.2
5.3
5.6
5.8
6.0
6.6
7.0
7.9
4.8
5.2
6.3
ns
Notes:
Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is
measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin
clock-to-out delay for clocked outputs for FAST mode configurations.
Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see Figure 1.
Speed Grade
All
-3
-2
-1
-09
-08
Units
Description
Symbol
Device
Min
Max
Global Early Clock to Output using
Output Flip Flop. Values are for
BUFGE #s 3, 4, 7, and 8.
TICKEOF
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
1.3
1.5
1.6
1.7
1.8
1.9
2.0
2.2
7.8
8.1
8.5
8.8
9.1
9.4
9.7
10.1
10.5
10.9
11.8
6.8
7.1
7.4
7.6
7.9
8.2
8.5
8.8
9.1
9.5
10.3
5.9
6.5
6.6
6.7
7.2
7.5
7.8
8.1
8.6
9.3
5.3
6.1
6.3
6.4
6.8
6.9
7.2
7.3
7.9
8.1
8.8
5.7
6.4
7.3
ns
Notes:
Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is
measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all
accessible CLB flip-flops. For designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined
by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin
clock-to-out delay for clocked outputs for FAST mode configurations.
Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see Figure 1.
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XC4013XL-2BG256M 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4013XL-2HT144C 功能描述:IC FPGA C-TEMP 3.3V 2SPD 144HQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現場可編程門陣列) 系列:XC4000E/X 標準包裝:1 系列:Kintex-7 LAB/CLB數:25475 邏輯元件/單元數:326080 RAM 位總計:16404480 輸入/輸出數:350 門數:- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA,FCBGA 供應商設備封裝:900-FCBGA(31x31) 其它名稱:122-1789
XC4013XL-2HT144I 功能描述:IC FPGA I-TEMP 3.3V 2SPD 144HQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現場可編程門陣列) 系列:XC4000E/X 標準包裝:1 系列:Kintex-7 LAB/CLB數:25475 邏輯元件/單元數:326080 RAM 位總計:16404480 輸入/輸出數:350 門數:- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA,FCBGA 供應商設備封裝:900-FCBGA(31x31) 其它名稱:122-1789
XC4013XL-2HT144M 制造商:XILINX 制造商全稱:XILINX 功能描述:XC4000E and XC4000X Series Field Programmable Gate Arrays
XC4013XL-2HT176C 功能描述:IC FPGA C 3.3V 2SPD 176HTQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現場可編程門陣列) 系列:XC4000E/X 標準包裝:1 系列:Kintex-7 LAB/CLB數:25475 邏輯元件/單元數:326080 RAM 位總計:16404480 輸入/輸出數:350 門數:- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA,FCBGA 供應商設備封裝:900-FCBGA(31x31) 其它名稱:122-1789