參數(shù)資料
型號(hào)： XC4013XL-1PQ240I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 5/16頁(yè)
文件大小： 0K
描述： IC FPGA I-TEMP 3.3V 1SPD 240PQFP
產(chǎn)品變化通告： Product Discontinuation 27/Apr/2010
標(biāo)準(zhǔn)包裝： 1
系列： XC4000E/X
LAB/CLB數(shù)： 576
邏輯元件/單元數(shù)： 1368
RAM 位總計(jì)： 18432
輸入/輸出數(shù)： 192
門數(shù)： 13000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 240-BFQFP
供應(yīng)商設(shè)備封裝： 240-PQFP（32x32）
R
DS005 (v2.0) March 1, 2013 - Product Specification
6-85
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Product Obsolete/Under Obsolescence
XC4000XL IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature)
.
Speed Grade
-3
-2
-1
-09
-08
Units
Description
Symbol
Device
Min
Clocks
Clock Enable (EC) to Clock (IK)
TECIK
All devices
0.1
ns
Delay from FCL enable (OK) active edge to
IFF clock (IK) active edge
TOKIK
XC4002XL
XC4013, 36, 62XL
Balance of Family
3.0
2.2
2.7
1.9
2.3
1.6
2.3
1.6
ns
Setup Times
Pad to Clock (IK), no delay
TPICK
XC4002XL
XC4013, 36, 62XL
Balance of Family
2.6
1.7
2.3
1.5
2.0
1.3
2.0
1.3
1.2
ns
Pad to Clock (IK), via transparent Fast Cap-
ture Latch, no delay
TPICKF
XC4002XL
XC4013, 36, 62XL
Balance of Family
3.2
2.3
2.9
2.0
2.5
1.8
2.4
1.7
1.6
ns
Pad to Fast Capture Latch Enable (OK), no
delay
TPOCK
XC4013, 36, 62XL
Balance of Family
1.2
1.0
0.9
ns
Hold Times
All Hold Times
All Devices
0
Global Set/Reset
Minimum GSR Pulse Width
TMRW
All devices
19.8
17.3
15.0
14.0
ns
Global Set/Reset
Max
Delay from GSR input to any Q
TRRI*
XC4002XL
XC4005XL
XC4010XL
XC4013XL
XC4020XL
XC4028XL
XC4036XL
XC4044XL
XC4052XL
XC4062XL
XC4085XL
9.8
11.3
13.9
15.9
18.6
20.5
22.5
25.1
27.2
29.1
34.4
8.5
9.8
12.1
13.8
16.1
17.9
19.6
21.9
23.6
25.3
29.9
7.4
8.5
10.5
12.0
14.0
15.5
17.0
19.0
20.5
22.0
26.0
7.0
8.1
10.0
11.4
13.3
14.3
16.2
18.1
19.5
20.9
24.7
10.9
16.2
20.4
ns
Propagation Delays
Pad to I1, I2
TPID
All devices
1.6
1.4
1.2
1.1
1.0
ns
Pad to I1, I2 via transparent input latch,
no delay
TPLI
XC4002XL
XC4013, 36, 62XL
Balance of Family
4.7
3.1
4.2
2.7
3.6
2.4
3.5
2.2
2.1
ns
Pad to I1, I2 via transparent FCL and in-
put latch, no delay
TPFLI
X4002XL
XC4013, 36, 62XL
Balance of Family
5.4
3.7
4.7
3.3
4.1
2.8
3.9
2.7
2.5
ns
Clock (IK) to I1, I2 (flip-flop)
Clock (IK) to I1, I2 (latch enable, active
Low)
FCL Enable (OK) active edge to I1, I2
(via transparent standard input latch)
TIKRI
TIKLI
TOKLI
All devices
XC4002XL
XC4013, 36, 62XL
Balance of Family
1.7
1.8
5.2
3.6
1.5
1.6
4.6
3.1
1.3
1.4
4.0
2.7
1.2
1.3
3.8
2.6
1.2
1.3
2.5
ns
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
* Indicates Minimum Amount of Time to Assure Valid Data.
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